Xilinx tunes tools for big FPGA

Xilinx tunes tools for big FPGAs
By Michael Santarini, EE Times
May 8, 2000 (7:23 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000508S0079

SAN MATEO, Calif.—FPGA tools will draw a step closer to their ASIC counterparts this week, when Xilinx Inc. releases a version of its Alliance Series software aimed at helping users efficiently design with multi-million-gate FPGAs.

Kenn Perry, senior director of software marketing at Xilinx, said the company typically releases its design software in advance of a new device family. The next big FPGA line, due out later this year, will contain 10 million FPGA gates, Perry said, and will thus require FPGA tools resembling those used in the ASIC design world.

"With our version 3.1i release, we believe we encapsulate all the tools needed to create a 10-million-gate FPGA within a single tool flow," he said.

Xilinx has included several ASIC-tool like features in version 3.1i. Design flow enhancements include modular design for teams of engineers working collaboratively, run-time improvements for timing clos ure, incremental design flows, and hierarchical floor planning for designs of up to 10 million gates.

Perry said Xilinx improved both the pushbutton and advanced tool flows in version 3.1i.

Less time on timing
In the pushbutton flow, the company added a non-timing-driven place and route feature that lets designers forgo spending time on timing analysis. The company also added an auto-time-specifying feature, which is said to deliver very fast clock speeds for non-timing-driven designs. And an HTML-based hierarchical timing report has been made the default in the pushbutton flow.

At the other extreme, the company has added several ASIC-design like features. A high-level floor planner lets engineers define area groups based on a design's hierarchy, thus simplifying floor planning for synthesis.

Engineers can also resize area groups without deleting or reapplying logic and can graphically assign I/Os to actual device pin locations.

The suite has a detailed floor planner so engi neers can create and modify macros.

These higher-level functions, according to the company, aid in integration with modular design methodologies and with register-transfer-level floor planners.

The floor planner includes a color-coded congestion viewer that lets users intelligently allocate resources to avoid potential problems.

Another advanced flow feature is modular design. According to Perry, the feature lets team members independently design, assign timing constraints for, synthesize and implement each module. The modules can be placed in the design at any time throughout the design cycle, the company claims, resulting in faster place and route run times and shorter time-to-timing-closure for large designs.

Another run-time improvement is obtained via the use of new algorithms for timing analysis and place and route. The advancements are said to yield up to a fourfold run-time reduction on Virtex designs of greater than 1 million gates and an average twofold run-time reduction on smalle r devices.

The algorithmic advancements also deliver performance improvements of up to 15 percent on existing Virtex architectures, said the company.

Looking more like the ASIC tool flow every day, the Alliance Series 3.1i software provides guided place and route, integrated with synthesis tools from Synopsys Inc., Exemplar and Synplicity.

According to the company, the guide feature allows a designer to make small changes in a portion the design without disturbing other portions. That capability is mandatory in multimillion-gate designs during the verification and debugging process.

The Alliance Series software provides architecture-specific device support for all Xilinx product families. The software runs on Windows and Unix platforms. Pricing starts at $1,495.