Time for Structured ASIC?
August 07, 2007
Introduced a few years ago as a cheaper replacement to FPGA, Structured ASIC looked for a while as a quick success story for fabless semiconductors manufactures. In fact Altera found it necessary to come out with its own line of structured ASIC devices derived from its Stratix FPGA line just to make sure they would not loose designs initially implemented in FPGA to another manufacturer when the customer achieved volume production.
In fact the segment grew much slower than anticipated and a few startups looking for fame and fortune in this market quickly disappeared. But as development costs and design risks increase at leading edge process nodes, designers are looking for any method or tool that will allow them to meet requirements, schedule, and cost targets. And so, structured ASIC are gaining interest as an implementation alternative.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Faraday Offers Peripheral Composer, the Fastest Time-to-Market Structured ASIC for Peripheral Interface Chips
- Need a Perfect Ethernet IP? Key ASIC's 0.13um 10/100 PHY IP Solution is Ready Now
- Sondrel creates unique modelling flow software to cut ASIC modelling time from months to a few days
- First Intel Structured ASIC for 5G, AI, Cloud and Edge Announced
- Is It Time to Forget about Huawei?
Breaking News
- Vector Informatik and Synopsys Announce Strategic Collaboration to Advance Software-Defined Vehicle Development
- Allegro DVT Launches its First AI-Based Neural Video Processing IP
- Weebit Nano fully qualifies ReRAM module to AEC-Q100 for automotive applications
- Rambus Enhances Data Center and AI Protection with Next-Gen CryptoManager Security IP Solutions
- Crypto Quantique demonstrating device security platform that accelerates CRA-compliant development
Most Popular
- Axelera AI Secures up to €61.6 Million Grant to Develop Scalable AI Chiplet for High-Performance Computing
- Arm vs. Qualcomm: The Legal Tussle Continues
- Baya Systems Revolutionizes AI Scale-Up and Scale-Out with NeuraScale™ Fabric
- Synopsys Introduces Virtualizer Native Execution on Arm Hardware to Accelerate Software-defined Product Development
- Imagination GPU Powers Renesas R-Car Gen 5 SoC