Cadence Selects Chipidea's USB 2.0 IP For Its SoC Functional Verification Kit

Update: MIPS Technologies Acquires Chipidea (August 27, 2007)

Electronic Design Solution Addresses Time-to-Market Risks for Consumer and Wireless System-on-Chip Designs for USB 2.0 Subsystem Integration and System Verification

LISBON, Portugal -- August 27, 2007 -- Chipidea®, the world's leading provider of analog/mixed-signal subsystems and intellectual property (IP), today announced that Cadence® Design Systems, Inc. (NASDAQ:CDNS - News), the leader in global electronic-design innovation, has chosen to license Chipidea's USB 2.0 OTG Link Controller and PHY for integration into the new Cadence System-on-Chip (SoC) Functional Verification Kit. By selecting Chipidea technology to be integrated into the real-world representative SoC design included with the kit, Cadence directly addresses the challenges associated with developing and verifying the hardware and software of a USB 2.0-enabled SoC.

The Chipidea USB 2.0 solution offers designers a proven architecture combined with a rich feature set, including charger detection and audio switch to provide the highest flexibility and the lowest power necessary for today's complex SoCs. Chipidea USB 2.0 solutions are available in any technology, offering customers the broadest and most versatile portfolio for their specific needs. In addition, Chipidea has a fully dedicated team to support the integration process in every step of the design.

"We selected Chipidea's USB 2.0 IP for our SoC Functional Verification Kit because it allows us to demonstrate robust connectivity and power features within a verification methodology context to customers designing complex wireless and consumer SoCs," said David Tokic, director, strategic marketing, Verification Division at Cadence.

The Cadence SoC Functional Verification Kit provides a proven end-to-end methodology covering block-level design verification to chip and system-level advanced verification, automating Cadence Incisive® Plan-to-Closure Methodology comprehension, adoption, and implementation. Delivered with applicability consulting, the kit provides complete and interactive guidance for performing predictable and repeatable verification of blocks, clusters, full chips, and SoCs, and enables design teams to quickly and easily adopt the Cadence Incisive® Plan-to-Closure Methodology. The new kit reduces risk in the verification of designs by providing a comprehensive set of best principles, practices, and procedures that increases productivity and project predictability and ensures overall system-level quality.

"As chip designs for the latest consumer products become more complex, and designers need to integrate more IP and functionality in less time, effective and metric-driven verification from plan to closure of these designs becomes even more critical," said Luis Laranjeira, director, Embedded Peripherals and Digital Design of Chipidea "We are pleased to work with Cadence on their SoC Functional Verification Kit, knowing that the inclusion of our USB 2.0 IP will help design teams integrating connectivity into their products, eliminating the risk of their verification process."

About Chipidea

Chipidea is the world's number one analog/mixed-signal merchant technology supplier targeting fast-growing market segments including wireless communications, digital media and consumer electronics. Chipidea supports blue-chip customers across the globe, has an impeccable reputation for delivering high-quality products and is known for its reliable execution. Chipidea licenses its technology to leading companies in all major markets, delivering everything from high-precision, and single-function blocks to full analog sub-systems. For more information: www.chipidea.com.