Acacia Semiconductor Announces a New Family of Best-in-Class High-Speed 10-bit ADC IPs Silicon Proven in a 130nm Process

Update: Acacia Semiconductor has been bought by S3 Group on October 31st, 2007.

CAPARICA, Portugal, August 28, 2007 -- Acacia Semiconductor, a leading supplier of low-power data converter IP, announced today the availability of a new family of ultra-low power, high-speed 10-bit ADCs IPs, silicon verified in a standard 130nm process and designed to enable semiconductor designers to differentiate end products and reduce system costs.

The new product family consists of six different ADC IPs that feature 10-bit resolution, single and dual channel solutions, sampling rates from 20MS/s up to 160MS/s and 300MHz sample-and-hold circuits. A comprehensive set of auxiliary circuits in the product family include voltage reference buffers with external decoupling for lowest possible power and internal decoupling for high speed operation at 120MS/s and above, low-noise bandgap references, internal precision current references, differential input clocking and duty cycle restoring.

The ADC IP parts (code named AS1080aV, AS1012aV and AS1016aV for the single channel solutions and AS1080bV, AS1012bV and AS1016bV for the dual channel versions) are suitable for a wide range of applications including most mobile TV standards, legacy Wi-Fi 802.11a/b/g, next generation Wi-Fi 802.11n including 40MHz channels, WiMAX fixed and mobile, flat-panel displays and video applications.

“We are extremely pleased with the silicon evaluation results obtained across all these new products. For example, the AS1080aV features sampling rates from 20MS/s up to 80MS/s and best-in-class power dissipation of only 19.9mW at 80MS/s, 10.6mW at 40MS/s and a mere 5.6mW at 20MS/s”, said Dr. Bruno Vaz, Team Leader for ADC Design.

“Furthermore, our top-end product, the AS1016aV, stands out as one of the highest-speed 10-bit ADC IPs available today, while featuring only 36mW at 160MS/s from a 1.2V supply and 56dB SNR, -67.2dB THD and 70.2dB SFDR measured for a 60MHz input signal. This is clearly the most energy-efficient 10-bit high-speed ADC IP available in the market”, Dr. Vaz continued.

“Our design team has accomplished a quite remarkable feat by achieving right-first-time silicon across the entire product family and furthermore demonstrating best-in-class power dissipation performance in every single ADC IP within the family”, commented Dr. Bernardo Henriques, CEO of Acacia Semiconductor.

“This achievement demonstrates our uniqueness in the analog IP market, that is a unique combination of experienced analog designers, innovative analog design techniques, a proprietary analog design optimization and sizing engine and a top-class silicon evaluation platform”, Dr. Henriques concluded.