Solution Enables Silicon Diagnosis without Access to Test Equipment SAN JOSE, Calif. — September 10, 2007 — LogicVision, Inc. (NASDAQ: LGVN), a leading provider of test and yield learning capabilities for the semiconductor industry, today announced Silicon Insight™, a new desktop silicon diagnostic solution. Silicon Insight, running on a Linux PC or laptop, interfaces to a customer’s device or performance board through simple USB-to-JTAG cable interface hardware to provide an interactive graphical environment for characterization, debug and diagnosis of silicon devices incorporating LogicVision’s embedded test IP. With Silicon Insight it is now possible to perform full device debug and diagnostics without the need to access or tie-up expensive automatic test equipment. This accelerates silicon debug and yield learning. LogicVision will demonstrate Silicon Insight at the 2007 International Test Conference, Oct 23-25, in Santa Clara, CA.
“By using LogicVision’s Silicon Insight product, PLX was able to easily characterize an embedded RAM in one of our latest devices,” said Adrian Arozqueta, DFT manager at PLX Technology, the market leader for PCI Express Bridges and Switches. “In addition to the advantages in cost and convenience of performing device diagnostics in the lab as opposed to on the production floor, we were able to complete the characterization of the RAM across multiple operating conditions and process corners within hours of the software installation.”
Silicon Insight works with LogicVision’s Memory BIST, Logic BIST, PLL BIST and SerDes BIST embedded test IP. It is based on LogicVision’s production-proven ETDiagnostics™ product family. Using Silicon Insight’s intuitive graphical environment, test and design teams can run a full suite of embedded test algorithms and diagnose their designs down to failing memory cells or logic gates. The USB-to-JTAG interface logic is off-the-shelf matchbook sized hardware and is included with Silicon Insight.
“Silicon debugging is not confined to a few seconds on the test floor. It has become a major bottleneck in getting working silicon to market,” said Farhad Hayat, VP of marketing at LogicVision. ”It involves collaboration between design and DFT teams in the lab, requiring easy access to the DFT infrastructure in the device. Silicon Insight brings device debug to the desktop instead of the production floor or tester lab, making it much more accessible to design teams. It’s a convenient and affordable solution for any size company.”
Silicon Insight is available in three configurations for Memory, Logic or Mixed-Signal diagnostics.
Silicon Insight-Memory provides a fully interactive graphical environment for diagnosing and characterizing memories tested using LogicVision’s memory BIST capabilities. The graphical environment provides a visual representation of the memory BIST resources within the device and the order in which they are to be executed. Failing memory, memory port, and memory I/O information is generated instantaneously at the touch of a button and is both displayed graphically and sent to a datalog file for future processing. Bit level failure information can also be generated for any failing memory. For each failure the tool displays: the failing memory port, the failing row and column addresses and bit position, the algorithm used to test the memory, and the phase of the algorithm in which the failure was detected.
Silicon Insight-Logic provides a fully interactive graphical environment for diagnosing and characterizing logic tested using LogicVision’s logic BIST capabilities. Four levels of automated logic diagnostics are provided. At all levels, both static and at-speed failures can be diagnosed:
• Core level: Identifies which physical layout regions contain failures.
• Trial level:Identifies which pseudo-random test patterns are failing within each core. The number of failing patterns to diagnose can be specified.
• Flip-flop level: Identifies which flip-flops in the design are capturing faulty values within each failing pattern. The number of failing flip-flops to diagnose per failing pattern can be specified.
• Gate level: Provides a report on the location of the suspected net, or nets, where defects can be found. This information can also be fed to third-party defect analysis tools.
Silicon Insight-MixedSignal provides a fully interactive graphical environment for diagnosing and characterizing mixed-signal circuits tested using LogicVision’s PLL or SerDes BIST. PLL diagnostic features include:
• Measurement of jitter, loop gain, lock range, and lock time
• Statistical analysis plots for measured parameters
SerDes diagnostic features are planned for future releases of the product and are expected to include:
• Measurement of many waveform, jitter, and jitter tolerance parameters, with sub-picosecond resolution, for selected amplitude, pre-emphasis, and equalization settings
• Measurement of bit error rate (BER) for any time interval
• Statistical analysis plots for measured parameters
Support for popular Automatic Test Equipment
In addition to enabling desktop diagnostics, Silicon Insight provides the option to interface directly with popular LVReady™ testers in a production or tester lab environment. LVReady ATE platforms include:
• Teradyne Catalyst
• Teradyne UltraFlex, Flex, J750
• Verigy 93000
• LTX Fusion
• Credence Duo/ Quartet
• Advantest T6000
Other ATE interfaces are available upon request.
Availability
Silicon Insight is in full production and available immediately.
About LogicVision Inc. LogicVision (NASDAQ: LGVN) provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at
www.logicvision.com.
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