Atmel Introduces Second Generation EDA Tool For Programmable System-On-Chips

SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 10, 2001-- Atmel® Corporation (Nasdaq:ATML - news) today introduced its second generation System Designer EDA tool suite for design of its FPSLIC(TM) family of programmable systems-on-chips (SoCs). System Designer 2.0 is the most comprehensive programmable SoC tool suite available providing fully integrated software (AVR® processor) & hardware (FPGA) co-design and co-verification for the implementation of embedded systems designs. Unique features specifically target embedded system designers and software engineers to help automatically create and verify FPGA logic without having expert knowledge of FPGAs or a hardware description language (VHDL or Verilog).

Atmel's AT94K series FPSLIC(TM) provides on a single chip the logic, processing, control, memory and I/O functions required for low power, high performance embedded systems applications such as industrial control, wireless infrastructure, point of sale and test equipment.

Design Flow Supports Embedded Systems - Unlike first generation programmable SoC EDA tools which focus specifically on FPGA design methodologies, System Designer offers features to support embedded system designers. The System Designer tool integrates a complete code development environment (compiler, debugger and instruction set simulator (ISS)) with a comprehensive suite of FPGA design tools. The FPGA programmable logic and AVR microcontroller tool suites are integrated seamlessly within a co-verification environment that allows the FPGA and AVR portions of the design to be verified concurrently. The designer has full visibility into the processor's program counter, memory, registers, and peripherals and into the performance of the FPGA, at every stage during the HDL simulation. Co-verification has been shown to reduce system development times by over 50%. Atmel is the only programmable SoC supplier to ship co-verification tools as part of their standard tool suite.

HDL Planner(TM) Simplifies Hardware Design - System Designer's HDL Planner module allows firmware developers who are not familiar with hardware description languages to rapidly create syntactically correct Verilog or VHDL designs for the embedded FPGA logic inside FPSLIC. Using a top down design flow, the designer creates logic and memory components using any of more than 50 point-and-click function generators. In addition, HDL Planner will automatically generate architecturally optimized layout and post layout VHDL or Verilog models for the FPGA portion of the design.

Fixed IP and Software Drivers - In addition to the Macro Generator soft IP solution FPSLIC also has pre-defined the interface logic between the AVR, extensive data SRAM and on chip FPGA resources -- simplifying and accelerating the embedded design process. System Designer includes C and assembly code modules which can be cut-and-pasted into the designer's application code for the fixed peripherals on FPSLIC, including 2 UARTs, 3 timer counters (PWMs) 2-wire serial interface and programmable I/O ports; further reducing development time and risk.

According to Martin Mason, Atmel's PSLI Product Marketing Manager, "The advent of programmable systems-on-chips offer the promise of shorter design cycles, lower power consumption, improved reliability, increased flexibility and lower system cost. However, the combination of embedding a high performance processor with an FPGA on a single device poses significant software and hardware design methodology challenges. Processors run code designed in C or assembly language, while FPGA designs are typically developed in VHDL or Verilog. The question is, "How do engineers assess the tradeoffs between the software and hardware, as well as design and verify programmable SOC devices?" We have crafted our second generation tool suite with the embedded system designers in mind -- automating as much as possible the generation and implementation of the FPGA code and providing pre-defined software and hardware solutions to accelerate system development."

"An issue facing every programmable SoC product offering is that the programmable logic embedded within a programmable SoC must be verified with the microcontroller software. Until now the only way to determine which code is being executed from the FPGA simulator was to model the microcontroller in an HDL simulator and reverse engineer the hexadecimal instructions using the processor data book. Very few designers want to engage in that exercise."

"Atmel's System Designer tool flows in a unified co-design environment, offering complete visibility into the AVR code, registers, memory, and peripherals, while simultaneously stepping through the HDL simulation of the FPGA hardware. The simulation may be stopped at any point and the designer may pinpoint the exact location in the VHDL code and the exact line of code being executed by the FPSLIC processor. System Designer 2.0 is the only EDA methodology for programmable SOC devices to successfully address these real hardware and firmware design implementation issues," Mason concluded.

Pricing and Availability - System Designer is available now with a complete FPGA and processor development flow including design entry, synthesis, simulation, place and route and bit-streaming utilities for the embedded FPGA logic. To address the embedded processor design requirements, System Designer includes the AVR processor assembler, debugger and instruction set simulator; and a comprehensive co-verification solution. FPSLIC System Designer is included in the ATSTK94 FPSLIC Starter Kit, which includes a development board, cables and documentation and can be licensed from $495.

About Atmel

Founded in 1984, Atmel Corporation is headquartered in San Jose, California with manufacturing facilities in North America and Europe. Atmel designs, manufactures and markets worldwide, advanced logic, mixed-signal, nonvolatile memory and RF semiconductors. Atmel is also a leading provider of system-level integration semiconductor solutions using CMOS, BiCMOS, bipolar SiGe, and high-voltage BCDMOS process technologies.

Requests may be sent via e-mail to literature@atmel.com or by visiting Atmel's website at www.atmel.com. For more information on FPSLIC, go to: http://www.atmel.com/atmel/products/prod39.htm

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