Tensilica Picks EVE's ZeBu for Validation of Diamond Video Core
Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Fast Emulation System Used for Conformance Testing, Codec Development, Multi-Processor Synchronization Validation
Santa Clara, Calif. -- September 18, 2007 -- EVE, the leader in hardware/software co-verification, today announced that Tensilica, Inc., used EVE’s ZeBu to validate the Diamond 38xVDO Video Engines.
Targeted at mobile handsets and personal media players (PMPs), Tensilica’s Diamond Standard Video Engines are fully programmable to support VGA and standard definition (SD, also known as D1) video codecs.
ZeBu (for Zero Bugs) gives Tensilica verification engineers an easy-to-use and affordable solution that combines the best aspects of traditional emulation and rapid prototyping systems. It is used in Tensilica’s system-level regression testing, hardware/software integration, application and codec development, conformance testing and profiling. ZeBu also proved useful in validating multi-processor synchronous debugging. In addition to allowing software engineers to validate codecs, ZeBu also helped Tensilica’s engineers find subtle bugs during product development related to clock tree issues missed during register transfer level (RTL) simulation.
“Our challenge in bringing our video solution to market was to concurrently design the optimized processor cores and software codecs,” says Beatrice Fu, senior vice president of Engineering at Tensilica. “ZeBu allowed us to validate changing codec and hardware revisions almost immediately. The result was a high confidence that our final product, really a combination of hardware and software, would just work.”
ZeBu is used during the system-integration phase of the design cycle where multiple logic blocks, multiple chips and embedded software must be verified simultaneously. Hardware design and software development teams can share the same system and design representation, and collaborate when debugging complex hardware/software interactions.
Architected with field programmable gate arrays (FPGAs), ZeBu is configured for designs from 12.5- to 100-million application specific integrated circuit (ASIC) gates in a compact, rack-mountable unit. It emulates designs with a speed of 20 megahertz (MHz) at the transaction level and in in-circuit emulation (ICE) or synthesizable testbench (STB) mode. It can be configured to accommodate up to 200-million ASIC gates through two interconnected units.
Adds Alain Raynaud, EVE’s technical director: “We’re quite proud of our strong partnership with Tensilica. Through this relationship, Tensilica has helped prove that ZeBu can increase engineering productivity, especially as a common platform for hardware and software engineers, thus reducing the time to market.”
About EVE
EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its United States headquarters are in Santa Clara, Calif. Telephone: (408) 855-3200. Facsimile: (408) 845-9209. Corporate headquarters are in Palaiseau, France. Telephone: (33) 1 64.53.27.30. Fax: (33) 1 64.53.27.40. Email: info@eve-team.com. Website: http://www.eve-team.com.
|
Related News
- Valens Semiconductor Picks Tensilica's Diamond Standard 108Mini for chip that Ensures High-Quality Home Audio-Video Networking
- Konica Minolta Adopts EVE's ZeBu Emulation Platform to Dramatically Accelerate Validation of Image Processing LSI Designs
- Morpho's MovieSolid and Morpho Video WDR Now Available on Cadence Tensilica Imaging/Vision DSPs
- Almalence Ports Optimized Image Processing Software onto Tensilica's New IVP Imaging/Video DSP
- Irida Labs and Tensilica Partner for Computer Vision Applications on Tensilica's New IVP Imaging/Video DSP
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |