Fujitsu and Denali Software Collaborate to Develop DFI Compatible DDR PHY Macro
"DDR DRAM memory system design has emerged as a significant design challenge that affects a wide range of applications, spanning communications, computing, networking, and consumer electronics such as digital audio-videos," said Brian Gardner, vice president of IP products at Denali Software. "A key part of the solution involves decoupling the DDR PHY design, which is highly process dependent and timing sensitive, from the DDR controller logic design, which is driven by system performance requirements. The DFI specification provides a clean boundary between these two memory system components, and enables developers to use best-in-class PHY and memory controller designs. Fujitsu's new DFI compatible DDR PHY designs are a demonstration of state-of-the-art solutions for ASIC development, and provide customers with a significant advantage in DDR memory system development."
The DFI compatible DDR PHY product, co-developed with Fujitsu VLSI Limited, is delivered as a macro to customers using Fujitsu's 90-nm process technology or further advanced technologies. In addition to 90-nm, Fujitsu is planning to utilize this DDR PHY product for other Fujitsu proprietary process technologies including generations previous to 90-nm. Furthermore, Fujitsu's DDR PHY macro has been verified with Denali's DFI compatible Databahn(TM) DDR controllers, enabling customers with a complete memory system solution.
"Denali Software is not only a leader in preparing the DFI specification, but also has a good track record for releasing many high-quality DDR controllers. Collaborating to verify the interface between Fujitsu's DDR PHY and Denali's DDR controllers shows a significant achievement in terms of providing customers with high-quality and interoperable DDR systems with low risk," said Yoshio Watanabe, General Manager of the IP Platform Solutions Division, Electronic Devices Business Unit of Fujitsu Limited.
About the DDR PHY Interface (DFI) Specification
The DFI specification was developed by expert contributors from recognized leaders in the semiconductor, IP, and electronic design automation (EDA) industries. The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with the goal of reducing costs for integrating DDR memory controller logic and DDR PHY interface while increasing performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. This enables reducing design and verification cost and time-to-market while increasing the potential for reusing the individual components that compose the memory system. The DFI Specification version 1.0 was released for production development in January 2007 and is available online at http://www.ddr-phy.org .
Time of Release
The DFI compatible DDR1 IF PHY up to 400 Mbps and the DFI compatible DDR2 IF PHY beyond 400 Mbps will be released at the end of September, 2007, and the end of November, 2007 for ASIC and COT using Fujitsu's 90 nm or further advanced process technologies, respectively.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com .
About Fujitsu Ltd
Fujitsu Limited (TSE: 6702; ADR: FJTSY) is a leading provider of customer-focused IT and communications solutions for the global marketplace. Pace-setting device technologies, highly reliable computing and communications products, and a worldwide corps of systems and services experts uniquely position Fujitsu to deliver comprehensive solutions that open up infinite possibilities for its customers' success. Headquartered in Tokyo, Fujitsu reported consolidated revenues of 5.1 trillion yen (US$43.2 billion) for the fiscal year ended March 31, 2007. For more information, please visit www.fujitsu.com.
|
Related News
- Denali Software and Tokyo Electron Device Unveil New DFI Compatible DDR2 SDRAM PHY for Xilinx FPGA
- Denali Software DDR SDRAM Controller IP and PHY Solution Integrated into STMicroelectronics' SPEAr Family of Microprocessors
- Netronome Systems Standardizes on Denali Software Design IP to Accelerate Design Cycles and Reduce Risks
- Toshiba Delivers DFI-Compatible DDR PHY to Speed Custom SoC Memory System Designs
- ARM, Denali, Intel, Rambus, Samsung, and Synopsys Collaborate on DDR PHY Interface Specification for DDR-DRAM Memory System Design
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |