Synopsys DesignWare USB 2.0 NanoPHY and PCI Express PHY IP Achieve Compliance in SMIC's 130-NM Process Technology
Silicon-Proven, Mixed-Signal IP Enables Easy Integration into SoCs
Optimized for high-volume, power-sensitive applications, the DesignWare USB 2.0 nanoPHY IP provides the best combination of small area and low power. The PHY's unique tunability enables high yield and robust interoperability by allowing designers to quickly adjust for process variation and system parasitics. The DesignWare USB 2.0 nanoPHY is part of a comprehensive solution for USB protocol implementation including OTG digital controllers, host controllers, and verification IP. The silicon-proven DesignWare USB OTG solutions are currently shipping in volume in leading consumer, computing and wireless products.
Compliant with PCI Express 1.1, the DesignWare PHY IP for PCI Express offers the lowest power consumption (up to 50 percent lower than that of competitive solutions), as well as significant performance margin on the receiver and small die area. Its advanced built-in diagnostics engine and ATE test vectors enable at-speed production testing of the PHYs. Additionally, the DesignWare PHY IP for PCI Express offer a number of dedicated lane configurations from x1 to x8 that support both wire-bond and flip-chip packages. The DesignWare PHY IP for PCI Express is part of a comprehensive silicon-proven PCIe solution which includes endpoint, dual mode, root complex and switch IP as well as verification IP.
"Synopsys provides our customers with industry-leading USB and PCIe IP that offers a wide range of advanced features combined with excellent technical support," said Paul OuYang, SMIC marketing and sales. "Combining Synopsys' certified, silicon-proven IP with our manufacturing process technology enables designers to achieve their time-to-market goals, while providing a fast, low-risk path to volume production."
"Working with SMIC to silicon-validate and certify our PCIe and USB IP in their 130-nm G process technology shows our ongoing support to provide customers with industry-leading standards-based connectivity IP," said John Koeter, senior director of marketing for IP and Services at Synopsys. "We understand the critical need to provide designers with high-quality, certified IP solutions that continually evolve with advanced process technologies."
Availability
The DesignWare USB 2.0 PHY IP, USB 2.0 nanoPHY IP and the PCI Express PHY IP for the SMIC's 130-nm process are available now.
About DesignWare Cores
Synopsys DesignWare Cores provide designers with silicon-proven, digital, and mixed-signal connectivity IP which is use in some of the world's most recognized products, including communications processors, routers, switches, game consoles, digital cameras, computers and computer peripherals. Provided as synthesizable RTL source code or in GDS format, these cores enable designers to create innovative, cost-effective system-on-chips and embedded systems. Synopsys provides flexible licensing options for the DesignWare Cores. Each core can be licensed individually or users can opt to license all the cores as part of one simple agreement. For more information on DesignWare IP, visit: http://www.designware.com/.
About Synopsys
Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading system and semiconductor design and verification platforms, IC manufacturing and yield optimization solutions, semiconductor intellectual property and design services to the global electronics market. These solutions enable the development and production of complex integrated circuits and electronic systems. Through its comprehensive solutions, Synopsys addresses the key challenges designers and manufacturers face today, including power management, accelerated time to yield and system-to-silicon verification. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
|
Search Silicon IP
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys DesignWare USB 2.0 nanoPHY and PCI Express 1.1 PHY IP First to Achieve Compliance in UMC's 65-Nanometer Process Technologies
- Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC's 65 Nanometer LL Process Technology
- Synopsys Delivers Industry's First Certified USB 2.0 PHY IP for Advanced 45-Nanometer Process
- Synopsys' New DesignWare Bridge IP for PCI Express to AMBA 2.0 AHB Connects Two Industry Standard Protocols
- Synopsys Introduces Validated USB 2.0 nanoPHY IP for TSMC'S Nexsys 90-LP Process
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |