Eureka spins cores tied to ARCtangent processor

The EP503 memory and peripheral controller interfaces between the processor's arbitration unit and provides access to external SDRAM, flash and PCI host bridge and peripheral slave devices. The EP453 PCI host bridge contains a bus master, a bus target and a configuration-initiator function to support instruction transfer in both directions. This, said the companies, lets an ARCtangent processor core access devices on the PCI bus (version 2.2), and lets a remote PCI bus master access the system's internal resources through the client-interface and memory-arbitration units.

Eureka said it optimized the EP503 to serve as the slave device for the ARCtangent bus-arbitration unit. The memory controller automatically handles SDRAM and flash timing such as row and column latency, precharge timing and data burst length, setting all of them on system reset.

The EP503 is said to support all industry-standard SDRAM organizations, ranging from 16- to 256-Mbit devices, and from x4 to x32 data widths.

The EP453, meanwhile, supports the PCI specification 2.2 protocol, and is designed for ASIC and FPGA implementations in various system environments. The companies said the bus interface unit performs all the data transfer functions necessary for the bus-mastering device to access data through the PCI bus. It supports burst-data transfer to maximize data bandwidth.

Eureka delivers the cores in RTL source code (Verilog or VHDL), and a testbench with test vectors and data sheet top-level design templates. Visit www.eurekatech.com/products/arc/default.htm.

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