Jasper Design Automation Announces JasperGold(R) Verification System v4.5 Featuring Liveness Property Support, Improved Modeling and Faster Engine Performance

Latest Release Improves Initialization Performance, Delivers Better Push-Button Mode Completion Rates and Provides Automatic Property Grouping for Faster Proofs

MOUNTAIN VIEW, Calif. -- October 3, 2007 -- Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today announced JasperGold® Verification System v4.5, a new release of the company's flagship formal verification solution that delivers support for liveness properties, enhanced engine performance and support for properties containing multiple clocks -- a new functionality important for modeling the industry's most sophisticated properties. In release 4.5, JasperGold also includes improved initialization performance for easier formal analysis and automatic property grouping for faster proofs.

In release 4.5, JasperGold delivers high-leverage, low-effort formal verification by deploying Jasper's unique Proof Accelerators(TM), Lossless Abstractions(TM), and patented Formal Scoreboard(TM), which provide more robust performance, increased ease-of-use and unmatched end-to-end proof capacity. These three powerful extensions complement JasperGold's unique Design Tunneling(TM) Architecture to dramatically improve formal verification performance while maintaining design integrity and simplifying coding requirements. Pre-defined formal-optimized generic algorithms are provided for common, hard-to-model design constructs such as data transport blocks, FIFOs, memories, etc. Jasper Proof Accelerators simply "plug-in" to an existing design, driving greater performance while still maintaining design integrity, since the RTL design is never modified. Jasper Lossless Abstractions automatically reduce proof complexity for counters and other constructs while retaining all information required for full verification of the design. Jasper's Formal Scoreboard is a unique, patented algorithm enabling the industry's only end-to-end full proof capability for data integrity properties.

"With its liveness property support, greater performance and powerful new modeling features, JasperGold v4.5 delivers sophisticated formal verification capabilities while minimizing the effort to attain high-leverage results," stated Craig Cochran, vice president of marketing at Jasper Design Automation. "These new capabilities have been driven by real-world deployment within our customers' verification environments, in turn propelling the company's methodology and technology development to make Jasper the leader in successful deployment of formal verification."

Pricing and Availability

JasperGold Verification System v4.5 is currently available. Call +1.650.966.0245 for complete details.

About Jasper Design Automation

Jasper Design Automation, a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers, is the leader in successful deployment of formal solutions in production verification environments. The company's flagship product, JasperGold Verification System, is the first verification product to deliver complete "deep formal" systematic verification, ensuring correctness where it matters most. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all use modes, without any testbench development. JasperGold Express, Jasper's formal ABV solution, provides the industry's leading "light formal" solution, complementing simulation-based approaches by accelerating bug hunting as well as coverage attainment. The JasperGold family quickly isolates bugs with a fast, static debugging capability, and then proves the absence of bugs, trimming design schedules. For further details on how to ensure guaranteed correctness where it matters most, please visit http://www.jasper-da.com.