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ARM gets serious in physical IP at 32 nm
Mark LaPedus, EE Times
(10/08/2007 9:00 AM EDT)
Santa Clara, Calif. -- Looking to get a jump on rivals like TSMC and Virage Logic, ARM Holdings plc last week pulled back the curtain on its 32-nanometer initiative for physical-intellectual property (IP).
At the same time, ARM warned that the dreaded shift to 32 nm will be an expensive and risky proposition, estimating that R&D costs will edge toward $75 million for a 32-nm design, compared with $20 million to $50 million at 45 nm.
ARM is best known for its processor cores, but physical IP--memory cores, phase-locked loops, standard cells and other IC building blocks for system-on-chip design--is critical to the company's growth. During a keynote address at the ARM Developers' Conference here last week, ARM CEO Warren East dropped hints about the company's bold 32-nm initiative for leading-edge physical IP.
(10/08/2007 9:00 AM EDT)
Santa Clara, Calif. -- Looking to get a jump on rivals like TSMC and Virage Logic, ARM Holdings plc last week pulled back the curtain on its 32-nanometer initiative for physical-intellectual property (IP).
At the same time, ARM warned that the dreaded shift to 32 nm will be an expensive and risky proposition, estimating that R&D costs will edge toward $75 million for a 32-nm design, compared with $20 million to $50 million at 45 nm.
ARM is best known for its processor cores, but physical IP--memory cores, phase-locked loops, standard cells and other IC building blocks for system-on-chip design--is critical to the company's growth. During a keynote address at the ARM Developers' Conference here last week, ARM CEO Warren East dropped hints about the company's bold 32-nm initiative for leading-edge physical IP.
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