Multicore gives more bang for the buck
(10/15/2007 9:00 AM EDT) -- EE Times
It has been clear for some time that a law of diminishing returns applies to the advancement of conventional processor architectures. Each new process geometry and microarchitecture delivers successively less in terms of performance gains: It is simply no longer possible to deliver Moore's Law by going faster.
At Intel, they have encompassed this truth by complementing Moore's Law with Pollack's Rule, named after Fred Pollack, director of Intel's microprocessor research labs. Pollack has observed that each new Intel architecture, starting with the i386, has required two to three times the silicon area (in a comparable process), while delivering a 1.4 to 1.7 times improvement in performance. In short, performance increases in proportion to the square root of complexity. In two generations, performance doubles for a fourfold increase in complexity; a 4X increase in speed (six years of Moore's Law) requires 16 times more transistor.
Meanwhile, many believe they have also determined what will prove to be the limiting factor in terms of process shrinks: not lithography or quantum physics, but the enormous power densities inherent in doing a great deal of processing work in a very small physical space (notoriously, the power density in a core has passed that of an iron, and is nearing that of a rocket nozzle).
E-mail This Article | Printer-Friendly Page |
|
Related News
- Microchip Technology Expands Processing Portfolio to Include Multi-Core 64-bit Microprocessors
- Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65
- Socionext Announces Collaboration with Arm and TSMC on 2nm Multi-Core Leading CPU Chiplet Development
- Semidynamics and SignatureIP create a fully tested RISC-V multi-core environment and CHI interconnect
- Andes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era