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Genesys Testware Adds Automated Batch-Mode Diagnosis and Characterization of Embedded Memories
FREMONT, Calif. -- October 17, 2007 -- Genesys Testware today announced the general availability of ArraytestMaker(TM) Diagnostics -- a software tool for automated batch-mode diagnosis and characterization of embedded memories. Automated diagnosis and characterization of embedded memories is essential for improving time-to-volume of system integrated circuits (IC) manufactured using processes with 65nm and finer geometries. Unlike competing solutions, ArraytestMaker Diagnostics works with any Automatic Test Equipment (ATE) without any hardware or software modification. Batch-mode operation simplifies test data management with globally distributed manufacturing test facilities. In contrast to other solutions, ArraytestMaker Diagnostics does not require any change in existing design flows because it works with any Test Access Port (TAP) controller.
"We are pleased to report the successful evaluation of ArraytestMaker Diagnostics on a real design," said Vinod Sutrave, President of Network Silicon, Inc. a leading IC design service provider. "Many of our mutual customers will find ArraytestMaker Diagnostics invaluable for fast ramp to volume production of system ICs."
ArraytestMaker Diagnostics processes data log files produced by applying ArraytestMaker test patterns on system ICs using ATE to produce full-failure maps, first-failure maps, and fuse maps. Full-failure maps denote the location of all failures in all embedded memories in a design. Full-failure maps require a longer ArraytestMaker diagnosis pattern to be applied on system ICs, and can be used to identify systematic yield loss mechanisms such as an inadequate on-chip power distribution network. First-failure maps denote the location of the first failure in each embedded memory in a design. First-failure maps can be used to identify the root cause of yield fluctuations in volume production. Fuse maps denote the physical location of each fuse that needs to be set to logical "1" state to repair all redundant memories in a design. Fuse maps can be used to improve yield by repairing redundant memories by blowing fuses using a laser.
"We are pleased to announce the commercial availability of ArraytestMaker Diagnostics," said Bejoy Oomman, President, Genesys Testware. "ArraytestMaker Diagnostics is a timely solution for IC designers facing yield ramp-up issues for chips manufactured in 65nm technology."
ArraytestMaker Diagnostics starts at $90,000 USD for a one year subscription.
Genesys will demonstrate ArraytestMaker Diagnostics during the International Test Conference 2007, October 23-25, in Santa Clara, California at the interoperability pavilion of the Magma Design Automation booth #320 at specific times. For more information visit http://www.magma-da.com/itc.
About Genesys Testware
Genesys Testware, Inc. provides tools to improve yield, quality and cost of nanometer ICs. Its products are all silicon-proven in various customer designs. For more information, please visit the company's web site at http://www.genesystest.com.
"We are pleased to report the successful evaluation of ArraytestMaker Diagnostics on a real design," said Vinod Sutrave, President of Network Silicon, Inc. a leading IC design service provider. "Many of our mutual customers will find ArraytestMaker Diagnostics invaluable for fast ramp to volume production of system ICs."
ArraytestMaker Diagnostics processes data log files produced by applying ArraytestMaker test patterns on system ICs using ATE to produce full-failure maps, first-failure maps, and fuse maps. Full-failure maps denote the location of all failures in all embedded memories in a design. Full-failure maps require a longer ArraytestMaker diagnosis pattern to be applied on system ICs, and can be used to identify systematic yield loss mechanisms such as an inadequate on-chip power distribution network. First-failure maps denote the location of the first failure in each embedded memory in a design. First-failure maps can be used to identify the root cause of yield fluctuations in volume production. Fuse maps denote the physical location of each fuse that needs to be set to logical "1" state to repair all redundant memories in a design. Fuse maps can be used to improve yield by repairing redundant memories by blowing fuses using a laser.
"We are pleased to announce the commercial availability of ArraytestMaker Diagnostics," said Bejoy Oomman, President, Genesys Testware. "ArraytestMaker Diagnostics is a timely solution for IC designers facing yield ramp-up issues for chips manufactured in 65nm technology."
ArraytestMaker Diagnostics starts at $90,000 USD for a one year subscription.
Genesys will demonstrate ArraytestMaker Diagnostics during the International Test Conference 2007, October 23-25, in Santa Clara, California at the interoperability pavilion of the Magma Design Automation booth #320 at specific times. For more information visit http://www.magma-da.com/itc.
About Genesys Testware
Genesys Testware, Inc. provides tools to improve yield, quality and cost of nanometer ICs. Its products are all silicon-proven in various customer designs. For more information, please visit the company's web site at http://www.genesystest.com.
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