Silicon Interfaces announces the release of its IEEE 1394 uVC Verification IP using Cadence IPCM Universal Reuse Methodology (URM)
The IEEE 1394 -1995/2000 link layer controller (from now on referred to only as 1394) provides connectionless acknowledged data transfer services between a source node and destination node where node is an addressable device attached to the serial bus with at least a minimum set of control registers.
The IEEE 1394 Function Controller uVC verifies designs that include IEEE 1394 Function Controller. This uVC consists of a complete set of elements for stimulating, checking, and collecting coverage information for the IEEE 1394 protocol, as well as thoroughly exercises the link controller.
The uVC supports IEEE 1394 PHY specification at the Physical side and Transaction Layer specification at the Host side. Data transmission can be configured to be at 100, 200 or 400 Mbps and can also be configured to be asynchronous or isochronous transaction.
|
Related News
- Silicon Interfaces announces the release of its Verification Methodology Manual (VMM) based USB 2.0 SystemVerilog Verification IP
- Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC
- Silicon Interfaces announces its OVM Based IEEE 1394 Link Layer Controller Verification IP
- Silicon Interfaces announces IEEE 1394 eVC (e Verification Component)
- Accellera Board Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard for Release
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |