Tensilica Enhances Entire Diamond Standard Processor Core Family, Offers New Features and Memory Power Reductions Up to 30 Percent

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

SANTA CLARA, Calif. – November 5, 2007 – Tensilica, Inc. today announced that it has enhanced its successful Diamond Standard processor product line, the lowest-power, most area-efficient and highest-performance licensable cores on the market. The new second-generation Diamond Standard processors include several new features including additional multiplier and divider functional units, several hardware optimizations that lower memory power by up to 30 percent, and an optional bridge to AXI-based AMBA systems.

“In their first year, the Diamond Standard cores have far exceeded our expectations,” stated Chris Rowen, Tensilica’s president and CEO. “Our customers have told us they were looking for the high performance, low power and small size of the Diamond Standard processor family. So we decided to make the family even faster, even lower power and even smaller. The second generation of Diamond Standard processor cores demonstrates our commitment to continued leadership in processor cores across the full range of control, DSP and media applications.”

The Diamond Standard Processor Family

The Diamond Standard processor product line includes five controller / CPUs and two digital signal processors (DSPs) that are being introduced or updated.

The controllers include:

• Diamond 106Micro – the smallest licensable 32bit, ultra-low power, cache-less RISC controller (announced today, see separate release).

• Diamond 108Mini Rev B – an ultra-low power, cache-less RISC controller with tightly coupled local memories, a hardware multiplier and divider, rich interrupt architecture and minimal gate count for low silicon cost.

• Diamond 212GP Rev B – a flexible mid-range RISC controller with DSP instructions, instruction/data caches, and tightly coupled local memories.

• Diamond 232L Rev B – a flexible mid-range applications processor with DSP instructions and a Memory Management Unit (MMU) for Linux OS support.

• Diamond 570T Rev B. – a high-performance, 3-issue static superscalar applications processor with over twice the performance per MHz of an ARM11 (based on EEMBC benchmarks).

The two DSPs in the updated Diamond Standard Processor family are

• Diamond 330HiFi Rev B– a low power 24-bit audio processor for all popular audio and speech codecs, based on the market-leading Xtensa HiFi 2 audio engine.

• Diamond 545CK Rev B– the highest performance licensable DSP on the market (based on BDTI Benchmarks) with a 3-issue VLIW (very long instruction word) processor.

Enhanced Features in the Second Generation Diamond Standard Processor Cores

The second generation Diamond Standard processors include three significant enhancements. First, the arithmetic capabilities of the controllers were significantly enhanced, reducing the need for external DSPs. An integer divider was added to the Diamond controllers (Diamond108Mini, Diamond 212GP, Diamond 232L, and Diamond 570T). This hardware divider significantly improves the performance of these processors on complex arithmetic applications like GPS, automotive applications, motor control, and engine control. A 32x32 single-cycle, pipelined multiplier has been added to the Diamond 108Mini, Diamond 212GP, and Diamond 232L processors, thereby improving the performance of these processors on common DSP algorithms (the Diamond 570T already had a multiplier).

Second, edge-triggered interrupts were added to all Diamond Standard processors, easing system design and giving faster interrupt response than level-triggered interrupts. Now, all Diamond Standard processors are available with up to 22 interrupts and 6 priority levels.

Third, Tensilica added support for relocatable exception vectors, which enables customers to change the memory location of exception handlers in software post-silicon. This gives more flexibility to the designer and eases system design.

Memory Power Reductions Up to 30 Percent

Tensilica made several changes that allow power on the memory interfaces to be reduced by up to 30 percent. One of the biggest changes included memory system optimizations that leave local data memories turned off for longer periods of time without negatively impacting performance. Also, Tensilica designed in additional power-down modes, including external power-down of the trace port control and on-chip debug modules, lowering overall system power.

“Low power is sometimes the biggest concern for SOC designers as they evaluate processor cores,” added Rowen. “We are committed to continue offering the industry’s best mix of low power and high performance in our cores.”

AMBA AHB and AXI Bridges Available

Tensilica now offers an optional AMBA® AXI™ bridge in addition to the AMBA® AHB-lite that has been available to Diamond Standard processor customers. These AHB and AXI bridges enable designers to easily integrate Diamond Standard cores into AMBA-based SOCs. All Tensilica Diamond Series controller and DSP cores are available with the native high-performance Tensilica PIF processor interface that is suitable for bridging to any on-chip bus (e.g. OCP, CoreConnect), or with an AMBA AXI or AHB-Lite interface. SOC designers therefore can choose any common on-chip bus and leverage existing infrastructure and peripheral component sets.

A Comprehensive Infrastructure of Tools and Peripheral Support

Tensilica provides a proven infrastructure for its Diamond Standard processor core family, and has added many new partners since the family was introduced early in 2006. This infrastructure includes software development tools directly from Tensilica as well as:

• Operating system support for ThreadX from Express Logic, the Nucleus Plus OS from Mentor Graphics, the Micrium uC/OS-II RTOS, and micro-iTRON from Sophia Systems

• Co-verification support for Mentor’s Seamless product

• Hardware prototyping boards from Avnet

• Emulation from ProDesign, S2C, Sophia Systems, and Yokogawa Digital Computer

• JTAG probe and Debugging support from Bytetools, FS2, Lauterbach, Macraigor Systems, Sophia Systems

• EDA tool support from Synopsys, Cadence and Magma

• ESL tool support from CoWare.

Availability

The second generation of the Diamond Standard processors is available now.

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.