English
Nanoscale chip verification: a massively analog problem?
Raul Camposano, President and CEO of Xoomsys
(11/05/2007 11:18 AM EST) -- EE Times
A while back, I moderated a panel entitled "The End of Traditional CMOS." This excellent discussion arrived at a somewhat optimistic conclusion: The rumors of the death of CMOS have been greatly exaggerated. The truth is, "simple" CMOS scaling has not been simple for a long time. Though it is getting harder, we have been dealing with new processes, materials, devices and circuits for decades, and we will continue to find appropriate process "enhancements." The trajectory of current manufacturing technology can reasonably be expected to get us to about 20 nm.
This brings us to the question, as "'traditional" CMOS manufacturing enables minimum geometries in the range of 10-100 nm, will "'traditional" CMOS verification enable us to deal with the manufacturing side effects that are found at these nanoscale depths? I submit to you that the answer is a resounding "No."
Each new technology node increases the number of available transistors geometrically; the time (and compute power) necessary to verify those transistors increases even faster. This by itself is not new. What is new (among other things, such as variability) is the increasingly analog nature of the problem: In the "good old days" of one-micron technology, interconnect hardly had to be considered for digital designs.
(11/05/2007 11:18 AM EST) -- EE Times
A while back, I moderated a panel entitled "The End of Traditional CMOS." This excellent discussion arrived at a somewhat optimistic conclusion: The rumors of the death of CMOS have been greatly exaggerated. The truth is, "simple" CMOS scaling has not been simple for a long time. Though it is getting harder, we have been dealing with new processes, materials, devices and circuits for decades, and we will continue to find appropriate process "enhancements." The trajectory of current manufacturing technology can reasonably be expected to get us to about 20 nm.
This brings us to the question, as "'traditional" CMOS manufacturing enables minimum geometries in the range of 10-100 nm, will "'traditional" CMOS verification enable us to deal with the manufacturing side effects that are found at these nanoscale depths? I submit to you that the answer is a resounding "No."
Each new technology node increases the number of available transistors geometrically; the time (and compute power) necessary to verify those transistors increases even faster. This by itself is not new. What is new (among other things, such as variability) is the increasingly analog nature of the problem: In the "good old days" of one-micron technology, interconnect hardly had to be considered for digital designs.
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