2.5D GPU / 2D & 3D Vector Graphics (OpenVG) Accelerator - D/AVE HD
Nanoscale chip verification: a massively analog problem?
(11/05/2007 11:18 AM EST) -- EE Times
A while back, I moderated a panel entitled "The End of Traditional CMOS." This excellent discussion arrived at a somewhat optimistic conclusion: The rumors of the death of CMOS have been greatly exaggerated. The truth is, "simple" CMOS scaling has not been simple for a long time. Though it is getting harder, we have been dealing with new processes, materials, devices and circuits for decades, and we will continue to find appropriate process "enhancements." The trajectory of current manufacturing technology can reasonably be expected to get us to about 20 nm.
This brings us to the question, as "'traditional" CMOS manufacturing enables minimum geometries in the range of 10-100 nm, will "'traditional" CMOS verification enable us to deal with the manufacturing side effects that are found at these nanoscale depths? I submit to you that the answer is a resounding "No."
Each new technology node increases the number of available transistors geometrically; the time (and compute power) necessary to verify those transistors increases even faster. This by itself is not new. What is new (among other things, such as variability) is the increasingly analog nature of the problem: In the "good old days" of one-micron technology, interconnect hardly had to be considered for digital designs.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
- INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with Siemens' advanced analog and mixed-signal EDA technology
- EDA Tools for Analog: Where Do I Go From Here?
- What's driving the acquisitions in the analog design realm?
- Is analog IC fab renaissance in the works?
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks