eSilicon Ramps 65Nm Design Engagements With Multiple Customers

SUNNYVALE, Calif. – Nov. 27, 2007 – eSilicon Corporation, a pioneering semiconductor Value Chain Producer (VCP), today announced that it is actively engaged on multiple customer designs using its previously demonstrated production-ready 65nm design methodology. The methodology leverages the cost and performance benefits of 65nm manufacturing processes and addresses the broad range of challenges and issues associated with moving to that process node

"New ASSP/ASIC design activity continues to grow at the leading-edge process nodes," said Jordan Selburn, principal analyst, iSuppli Corp. "Our research shows that design activity at 65nm will increase strongly through at least 2009, at which point it will have moved thoroughly into the mainstream and account for more designs than any other technology node. Furthermore, 2007 and 2008 design starts at 65nm will generate more than $15 billion in chip revenues in 2010."

"We are seeing significant demand for chips developed for advanced process nodes and customers large and small are looking for expertise to help them make that move,” said Hugh Durdan, VP of Marketing, eSilicon. "65nm has become the technology of choice for a wide range of applications. We are actively designing 65nm chips for a number of customers, as they feel that this is the best manufacturing process for their low-power, high-complexity designs.”

eSilicon first demonstrated its 65nm design expertise with its pre-hardened ARM926EJ™ processor core (New eSilicon HardCore Program Shortens Development Cycles – June 18, 2007). The company used its design methodology to optimize an ARM926EJ-S™ core with 8K of instruction and 8K data cache in the TSMC 65GP process, achieving performance of 750MHz and an area of 0.84 sq. mm with six layers of metal. The core was implemented using a complete, production-worthy timing sign-off including crosstalk and OCV, contains design-for-test (DFT) structures such as Scan and Memory BIST, and is design-for-manufacturability (DFM) compliant.

A key aspect of the eSilicon® 65nm design flow is built-in support for DFM. The methodology considers DFM aspects at each step of a chip's physical design, such as placement, routing and clock-tree synthesis, resulting in a robust solution that is easier and faster to manufacture and ramp into volume production.

Due to the increasing importance of designing for low power, the eSilicon 65nm design flow also addresses both dynamic and leakage power. Dynamic power is managed by using voltage islands and multiple voltage supplies; leakage power is managed by using multi-Vt libraries and power switches to shut down sections of the chip. Multi-Threshold CMOS (MTCMOS) cells are also available to address leakage.

For more information about eSilicon's 65nm design capabilities, please contact a local eSilicon sales representative or visit www.esilicon.com.

About eSilicon

eSilicon, a pioneering semiconductor Value Chain Producer (VCP), provides a comprehensive suite of design, productization and manufacturing services, enabling a flexible, low-cost, lower-risk path to volume production. The company delivers chips to system original equipment manufacturers (OEMs) and fabless semiconductor companies who serve a wide variety of markets including the consumer, computer, communications and industrial segments. eSilicon – Enabling Your Silicon Success™. For more information, visit www.esilicon.com.

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