English
Effort behind reusing IP blocks is underestimated
Anne-Francoise Pele, EE Times
(12/06/2007 4:27 PM EST)
GRENOBLE -- When intellectual property (IP) reuse entered the IC design paradigm more than ten years ago, the semiconductor industry expressed high expectations. IP reuse was indeed seen as a way to foster development productivity and output that would eventually offset the design productivity gap. Based on 1,200 benchmarked IC projects from more than 35 companies, Ron Collett, president and CEO of Numetrics Management Systems, Inc. (Cupertino, California), gave his views on how to achieve maximum IP reuse leverage.
"There are good and bad news about the reuse situation," stated Collett at the IP 07 Conference, organized by Design & Reuse SA, this week in Grenoble. Over the past ten years, reuse leverage more than doubled, and more reuse tends to translates into less project effort, shorter cycle times as well as fewer spins and less schedule slip.
Still on the positive side, Collett indicated that the average transistor count per block is growing and the number of blocks per chip is rising.
Moving to bad news, Collett noted that the average team size has doubled between the years 2000 and 2006. Collett also deplored that the semiconductor industry has serious schedule slip problems. About 85 percent of all IC projects miss their original schedule. "This is chaos. The average schedule slip is 44 percent, and high schedule slip means poor schedule predictability," he asserted.
(12/06/2007 4:27 PM EST)
GRENOBLE -- When intellectual property (IP) reuse entered the IC design paradigm more than ten years ago, the semiconductor industry expressed high expectations. IP reuse was indeed seen as a way to foster development productivity and output that would eventually offset the design productivity gap. Based on 1,200 benchmarked IC projects from more than 35 companies, Ron Collett, president and CEO of Numetrics Management Systems, Inc. (Cupertino, California), gave his views on how to achieve maximum IP reuse leverage.
"There are good and bad news about the reuse situation," stated Collett at the IP 07 Conference, organized by Design & Reuse SA, this week in Grenoble. Over the past ten years, reuse leverage more than doubled, and more reuse tends to translates into less project effort, shorter cycle times as well as fewer spins and less schedule slip.
Still on the positive side, Collett indicated that the average transistor count per block is growing and the number of blocks per chip is rising.
Moving to bad news, Collett noted that the average team size has doubled between the years 2000 and 2006. Collett also deplored that the semiconductor industry has serious schedule slip problems. About 85 percent of all IC projects miss their original schedule. "This is chaos. The average schedule slip is 44 percent, and high schedule slip means poor schedule predictability," he asserted.
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