English
Staccato Communications Selects Denali's Verification IP for Next-Generation WiMedia Products
High-Quality Verification IP Assures Compliant and Low-Risk Implementation for Industry-Leading Ripcord Single-Chip CMOS Ultra Wideband (UWB) Products
PALO ALTO, Calif. -- Jan. 8, 2008 -- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Staccato Communications has adopted PureSpec(TM) verification IP (VIP) to verify compliance with the latest protocol specifications and validate interoperability on their next generation single-chip all-CMOS WiMedia UWB ICs. Staccato's verification engineers chose Denali PureSpec VIP for its high-quality and seamless integration into their design and verification environment, providing a reliable and comprehensive framework for accelerating design cycle times.
"There is an increasing proliferation of devices that demand high bandwidth connectivity, and Staccato's Ripcord® UWB products deliver high data rate, lowest cost and longest battery life, enabling a cable-like wireless equivalent and new usage models," remarked Steven Larky, vice president of Engineering at Staccato Communications. "In order to achieve these goals in a very aggressive single-chip all-CMOS implementation, Denali was our first choice for their expertise and high-quality IP. We have reaped significant benefits from Denali's high-quality models and their reliable verification IP as it has helped us find critical bugs in our RTL as well as several bugs in our vendor supplied RTL IP, thus minimizing our overall time-to-market."
Staccato's Ripcord product family is comprised of single-chip, all-CMOS solutions for WiMedia UWB applications such as Wireless USB, Next-Generation Bluetooth, and WiMedia IP. Ripcord's high-level of integration minimizes design risk, lowers system cost and accelerates customers' time-to-market by consolidating all hardware and software components necessary to support multiple simultaneous protocols at 480 Mbps.
"Denali understands the challenges facing design and verification teams, including reaching time-to-market timelines while minimizing the impact on engineering resources," states David Lin, vice president of marketing at Denali Software. "Our customers, such as Staccato, confidently use our high-quality verification IP so that their designs can meet protocol compliance and significantly shorten the verification time required to bring their product to market."
About Denali PureSpec
Denali's PureSpec verification IP is the most widely used product for verifying functionality, compliance and interoperability of standard interfaces at the pre-silicon stage of chip or IP core development. PureSpec verification IP includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all components in the topology, including the host and one or multiple devices. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design. For more info about PureSpec and its benefits in your next design, visit: http://www.denali.com/products/vip.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
PALO ALTO, Calif. -- Jan. 8, 2008 -- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Staccato Communications has adopted PureSpec(TM) verification IP (VIP) to verify compliance with the latest protocol specifications and validate interoperability on their next generation single-chip all-CMOS WiMedia UWB ICs. Staccato's verification engineers chose Denali PureSpec VIP for its high-quality and seamless integration into their design and verification environment, providing a reliable and comprehensive framework for accelerating design cycle times.
"There is an increasing proliferation of devices that demand high bandwidth connectivity, and Staccato's Ripcord® UWB products deliver high data rate, lowest cost and longest battery life, enabling a cable-like wireless equivalent and new usage models," remarked Steven Larky, vice president of Engineering at Staccato Communications. "In order to achieve these goals in a very aggressive single-chip all-CMOS implementation, Denali was our first choice for their expertise and high-quality IP. We have reaped significant benefits from Denali's high-quality models and their reliable verification IP as it has helped us find critical bugs in our RTL as well as several bugs in our vendor supplied RTL IP, thus minimizing our overall time-to-market."
Staccato's Ripcord product family is comprised of single-chip, all-CMOS solutions for WiMedia UWB applications such as Wireless USB, Next-Generation Bluetooth, and WiMedia IP. Ripcord's high-level of integration minimizes design risk, lowers system cost and accelerates customers' time-to-market by consolidating all hardware and software components necessary to support multiple simultaneous protocols at 480 Mbps.
"Denali understands the challenges facing design and verification teams, including reaching time-to-market timelines while minimizing the impact on engineering resources," states David Lin, vice president of marketing at Denali Software. "Our customers, such as Staccato, confidently use our high-quality verification IP so that their designs can meet protocol compliance and significantly shorten the verification time required to bring their product to market."
About Denali PureSpec
Denali's PureSpec verification IP is the most widely used product for verifying functionality, compliance and interoperability of standard interfaces at the pre-silicon stage of chip or IP core development. PureSpec verification IP includes a configurable bus functional model (BFM), protocol monitor, and complete assertion library for all components in the topology, including the host and one or multiple devices. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design. For more info about PureSpec and its benefits in your next design, visit: http://www.denali.com/products/vip.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
|
||||||
Related News
- Synopsys Delivers Industry's First Ethernet 800G Verification IP for Next-Generation Networking and Communications Systems
- Synopsys Delivers Industry's First Ethernet 400G Verification IP for Next-Generation Networking and Communications Systems
- Wintegra Selects Denali's Verification Software for Design of Next-Generation Access Processors
- Magnum Semiconductor Selects Denali's Verification Software for Design of Next-Generation Digital Video Chips
- Synopsys Announces Industry's First JEDEC DDR5 Verification IP for Next-Generation DRAM/DIMM Designs
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |