Synfora Integrates PICO Express with CoWare ESL 2.0 Solutions
MOUNTAIN VIEW, Calif.-- January 16, 2008 --Synfora, Inc., a premier provider of algorithmic synthesis tools used to design systems-on-chips (SoCs), announced today that its models are now plug-and-play with the Platform Architect design environment from CoWare®, the leading supplier of platform-driven electronic system-level (ESL) design software and services. Joint customers will use Synfora’s PICO Express™ to create synthesizable RTL and the corresponding transaction-level SystemC models from an untimed C algorithm for product-specific intellectual property (IP), and reuse them in combination with other ESL models in CoWare’s Platform Architect to capture the entire product platform at the system-level. As a result, virtual hardware platforms for platform architecture design, performance verification, and software development can be more efficiently modeled and more easily maintained to reflect the latest hardware design of new IP, saving valuable design time and resources.
Synfora’s PICO platform is a system of tools and IP that create complex application engines from sequential, untimed C algorithms. These application engines – integrated hardware/ software sub-systems – can be rapidly and consistently integrated into a platform-based SoC. PICO enables design teams to predictably deliver complex SoCs by reducing cycle time, improving the ability to respond to late changes in specifications and partitioning the design into manageable sub-systems.
For platform-driven ESL design, CoWare Platform Architect is the leading SystemC-based graphical environment for capturing the entire product platform. CoWare ESL 2.0 solutions speed the concurrent design of SoC hardware and software. The created model can then be used for platform architecture design and verification and software development.
“With the new Synfora integration, SoC platform integrators and subsystem designers can derive even greater benefits from CoWare’s ESL 2.0 solutions,” said Patrick Sheridan, director of marketing at CoWare. “Application sub-systems designed with Synfora PICO Express are integrated into the entire platform designed with CoWare Platform Architect. CoWare is pleased that Synfora’s automatically-generated TLM models ease this design task for our mutual customers.”
“This joint solution meets increasing customer demand,” said Simon Napper, Synfora president and CEO. “PICO Express automatically produces SystemC transaction-level models from a C application, saving the time and resources that would be expended if these were written manually. Customers have been requesting a solution where PICO-generated SystemC models work in the context of CoWare’s Platform Architect and inter-operate with other SystemC models.”
About Synfora
Founded in 2003, Synfora Inc. is the leading provider of algorithmic synthesis tools used to design complex systems-on-chips (SoCs. Synfora’s technology helps to reduce design costs and dramatically speed chip development and reduce time-to-market. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the IC design market. The company’s investors are ATA Ventures, Foundation Capital, Wafra and U.S. Venture Partners. For latest information on Synfora, please visit http://www.synfora.com.
|
Related News
- Ricoh Deploys CoWare ESL 2.0 Solutions for Architecture Optimization and Pre-Silicon Software Development
- Hifn Selects CoWare ESL 2.0 Solutions for Design and Performance Optimization of Next-Generation Applied Services Processors
- Freescale Delivers Virtual Platforms to Continental Using CoWare ESL 2.0 Solutions
- CoWare and Sonics Release ESL 2.0 Upgrade of Joint Flow
- CoWare and Tensilica Integrate Diamond Standard 106Micro with CoWare ESL 2.0 Technology
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |