QuArc launches digital video codec core
QuArc launches digital video codec core
By Junko Yoshida, EE Times
March 22, 2000 (12:14 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000322S0010
SANTA CLARA, Calif. Startup QuArc Inc. launched a DV-based video encoder and decoder core at the IP2000 Conference this week. The company expects the core, named Videris-DV, to be integrated into IEEE-1394 ICs as well as digital camcorders. DV is a digital video compression standard originally developed as an acquisition format and now used broadly in digital camcorders and editing machines. The Videris-DV uses the same data-driven processing architecture as the high-definition MPEG-2 video decoder core that QuArc introduced late last year. Each block, embedded with a small amount of memory, can autonomously operate as an object without intervention by an external microcontroller. Use of this architecture yields "a very small, high-performance DV core with lower power consumption," said Ron Richter, vice president of sales and marketing at QuArc, based here. Beyond camcorders Thus far, t he market for DV codecs has been totally dominated by Japanese semiconductor vendors. However, several U.S. companies are starting to challenge that hegemony, in the belief that even if their DV chips don't find sockets in camcorders, they might find use in a growing list of consumer appliances. Products ranging from personal video recorders to digital TVs and set-top boxes now call for DV decoding or DV-to-MPEG-2 transcoding capabilities. As DV camcorders become more prevalent, "DV becomes something you'll have to have," said Richter. Especially in cases where consumers are to plug their DV camcorders into digital TV or any other digital appliances, system vendors will need IEEE-1394 interface ICs to integrate DV decoding or transcoding capabilities. QuArc's intellectual-property (IP) core supports all the variations of DV codecs. These include DV 25 (standard definition), the SMPTE314M 25- and 50-Mbit/second standards (formerly known as DVCPRO-25 and DVCPRO-50), and DV-SDL for long-play support. In addition, Videris-DV implements what the company calls the QuArc DV, or QDV, extension. QDV was designed "to give flexibility to users," said Kris Monsen, design manager at QuArc, so that they can specify their own preferred compression rate, from 8 to 80 Mbits/s, to optimize storage space or encoding quality. The QDV extension also supports square-pixel formats for NTSC (640 x 480) and PAL (768 x 576). For content creators developing for progressive-scan displays such as a PC monitor, video can be created in the native screen format, with no aspect ratio scaling required, thus making it easier to overlay graphics. QuArc will make Videris-DV available either as an encoder/decoder or as a decode-only IP core. The gate count for Videris-DV is 60,000 to 70,000 gates, said Richter. If not including encoding capability, "you can save about 6,000 gates," he added. The core, however, needs to be integrated with local SRAM, which is 2,048 bytes in total. "With the low gate count and low power co nsumption, we think our core can go into not only handheld camcorders but also IEEE-1394 chips and MPEG-2 encoder ICs," said Richter. The core is capable of real-time encoding of a single video stream, or decoding two or more DV-compressed video streams, when semiconductors that incorporate it use an 81-MHz clock. The core does not include audio capability. Along with DV pioneers Divio Inc. (Sunnyvale, Calif.), a leading DV codec company, and C-Cube Microsystems (San Jose, Calif.), other companies also appear to be integrating DV support in their IC products. Stephen Solari, vice president of sales and marketing at iCompression (Santa Clara), said that his company's upcoming MPEG-2 IC features DV-to-MPEG-2 transcoding capability. The chip has just taped out, Solari added. QuArc will provide its semiconductor customers with a complete video hardware design solution including gate-level net-list, bit-accurate C modules, functional-test bit streams, Verilog simulation shells and support scripts, do cumentation and Verilog source code. The company will make Videris-DV available to licensed customers in July. Meanwhile, QuArc, which has eight employees, has signed up its first customer for the high-definition MPEG-2 video decoder IP core, according to Sorin Cismas, president and CEO. "We are in discussion with some more [potential customers] right now," he said. The privately held company, originally funded by Cismas with no outside financing, is beginning to look for investment by venture capitalists. Cismas created QuArc based upon his experience as a co-founder of CompCore Multimedia, the first company to develop MPEG-2 video cores.
Related News
- eInfochips Launches HD Codecs - H.264 AVC and H.264 SVC - for Digital Media Processors From Texas Instruments
- MosChip Launches System-on-a-Chip (SoC) Processor for Digital Content Management in Camcorders, DVRs, Blu-Ray Disc Recorders, Video Editors and other AV Storage Devices
- Texas Instruments Launches New Development Platform for DaVinci Technology to Speed Development of Digital Video Products
- Mobilygen Launches the Industry's Lowest Power Single-Chip H.264 CODEC Chip Providing TV-Quality Video for Mobile Products
- Pixelworks Launches PWBSP-16 Broadband Signal Processor IC for High-Volume, Video-Centric Consumer Applications; Completely Programmable System-on-chip IC Delivers Multi-codec Solution for High-quality IPTV Video at a Competitive Price
Breaking News
- Kudelski IoT and PUFsecurity Combine IoT Security Strengths to Meet the Challenges of Increasing Global Regulation
- Alphawave Semi Joins UALink™ Consortium to Accelerate High-Speed AI Connections
- AST SpaceMobile and Cadence Collaborate to Advance the World's First and Only Planned Space-Based Global Cellular Broadband Network
- Intel CEO's Departure Leaves Top U.S. Chipmaker Adrift
- Post-Quantum Cryptography: Moving Forward
Most Popular
- Intel Announces Retirement of CEO Pat Gelsinger
- Tenstorrent closes $693M+ of Series D funding led by Samsung Securities and AFW Partners
- Lip-Bu Tan quit Intel board after "differences" with CEO, says Reuters
- MIPS Releases P8700, Industry's First High-Performance AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles
- Arteris Deployed by Menta for Edge AI Chiplet Platform
E-mail This Article | Printer-Friendly Page |