English
IP Adventures in EDA
By Gabe Moretti, edadesignline.com
March 13, 2008
By their own actions in the last few weeks, Mentor, Magma, and Cadence, have reopened the debate on whether or not IP belongs in EDA. Their answers respectively are: no, yes, and "on my own terms".
It was about a year ago that Michael Santarini and I had the last of a number of discussions on the topic: Michael was against the idea and I was defending EDAC's decision to include IP revenues in their Market Statistics Summary Report. My argument was based on historical facts. Long before the concept of Fabless Semiconductor Company was invented, Synopsys began to sell IP blocks under the DesignWare brand. If I remember correctly it was 1990, but certainly no later than 1991. The blocks were simple compared to what is available now, and the primary reason for selling them was to give a hand to designers still struggling with logic synthesis. Design Compiler was a tool at times difficult to use, both because it was new and because designers had never created synthesizable logic before. Will EDAC continue to include the IP market in the report? I think it depends on Cadence: read on.
March 13, 2008
By their own actions in the last few weeks, Mentor, Magma, and Cadence, have reopened the debate on whether or not IP belongs in EDA. Their answers respectively are: no, yes, and "on my own terms".
It was about a year ago that Michael Santarini and I had the last of a number of discussions on the topic: Michael was against the idea and I was defending EDAC's decision to include IP revenues in their Market Statistics Summary Report. My argument was based on historical facts. Long before the concept of Fabless Semiconductor Company was invented, Synopsys began to sell IP blocks under the DesignWare brand. If I remember correctly it was 1990, but certainly no later than 1991. The blocks were simple compared to what is available now, and the primary reason for selling them was to give a hand to designers still struggling with logic synthesis. Design Compiler was a tool at times difficult to use, both because it was new and because designers had never created synthesizable logic before. Will EDAC continue to include the IP market in the report? I think it depends on Cadence: read on.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- MosChip selects Cadence tools for the design of HPC Processor "AUM" for C-DAC
- Silvaco Inc. Achieves ISO 9001 Certification for Comprehensive Suite of TCAD, EDA, and IP Products
- China's EDA startup X-Epic forced to lay off staff, says report
- Altair Signs Agreement to Acquire Metrics Design Automation Inc. Expands Footprint in EDA Industry
- Siemens collaborates with Samsung Foundry to expand 3D-IC enablement tools, optimize other EDA solutions for foundry's newest processes
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models