English
Bluetooth low energy v5.4 Baseband Controller, Protocol Software Stack and Profiles IP
Mentor Graphics Expands Questa Functional Verification Platform with Questa Codelink for Processor-Driven Tests
WILSONVILLE, Ore. -- March. 27, 2008 - Mentor Graphics Corporation today announced immediate availability of the Questa® Codelink™ product, an addition to the Questa Functional Verification Platform designed to speed the validation of ASICs containing one or more embedded processors. The Questa Codelink product is an integrated, source-level debug environment targeting processor driven tests.
Use of sign-off accurate, RTL processor models to drive cycles into multi-core SoC designs is a common practice among hardware verification engineers. This method of test is identical to the SoC’s actual operation and provides highly effective functional verification. A major limitation to this approach is the lack of an effective debug environment. Isolating the cause of a failing processor driven test is a tedious and time consuming process as RTL processor models delivered by the core vendor provide little or no debug visibility.
To advance the use of processor driven test, Mentor developed Questa Codelink, a rich source-level debugger for RTL processor models supplied by ARM and MIPS. Codelink employs patent-pending technology which shadows the RTL model and generates a rich debug dataset. By presenting the user with a full view of software variables, call stack, registers, and memory, test failures can be isolated in minutes rather than days or weeks.
With one third of all SoC designs moving to multi-core in the next two years, it was important that Codelink support multi-core debug. Tracking multiple code threads and observing message passing via shared memory are key elements in debugging synchronization failures in multi-core systems. Codelink offers a variety of techniques for efficiently organizing and viewing the many representations of relevant data associated with multi-core source-level debug.
In addition, Codelink has the ability to log batch runs and debug interactively post-simulation, eliminating the need to rerun long simulations in order to debug them. Codelink replays a 15 hour simulation in 3 seconds, yielding highly interactive debug of large simulations. Codelink also supports stepping backwards through source or assembly while variables, memory, and registers views accurately reflect the state of the system.
“Over the past year our teaching customers like InterDigital, have been instrumental in helping us to refine and enhance the Codelink product,” said Serge Leef, general manager of Mentor’s System Level Engineering division. “What has emerged is a highly efficient debug environment for MIPS and ARM based SoCs.”
“Codelink has proven to be a highly cost-effective and efficient tool for us, particularly the replay feature,” said Kenneth Bartsch, Verification Lead at InterDigital. “Prior to Codelink, certain bugs required multiple one-day re-simulations to fully diagnose. With Codelink replay we simulate just one time, and isolate the failure (hardware or software) immediately. Both software and hardware engineers like the tool. Codelink was key to us taping out our new SlimChip™ SoC on schedule.”
Pricing and Availability
Use of sign-off accurate, RTL processor models to drive cycles into multi-core SoC designs is a common practice among hardware verification engineers. This method of test is identical to the SoC’s actual operation and provides highly effective functional verification. A major limitation to this approach is the lack of an effective debug environment. Isolating the cause of a failing processor driven test is a tedious and time consuming process as RTL processor models delivered by the core vendor provide little or no debug visibility.
To advance the use of processor driven test, Mentor developed Questa Codelink, a rich source-level debugger for RTL processor models supplied by ARM and MIPS. Codelink employs patent-pending technology which shadows the RTL model and generates a rich debug dataset. By presenting the user with a full view of software variables, call stack, registers, and memory, test failures can be isolated in minutes rather than days or weeks.
With one third of all SoC designs moving to multi-core in the next two years, it was important that Codelink support multi-core debug. Tracking multiple code threads and observing message passing via shared memory are key elements in debugging synchronization failures in multi-core systems. Codelink offers a variety of techniques for efficiently organizing and viewing the many representations of relevant data associated with multi-core source-level debug.
In addition, Codelink has the ability to log batch runs and debug interactively post-simulation, eliminating the need to rerun long simulations in order to debug them. Codelink replays a 15 hour simulation in 3 seconds, yielding highly interactive debug of large simulations. Codelink also supports stepping backwards through source or assembly while variables, memory, and registers views accurately reflect the state of the system.
“Over the past year our teaching customers like InterDigital, have been instrumental in helping us to refine and enhance the Codelink product,” said Serge Leef, general manager of Mentor’s System Level Engineering division. “What has emerged is a highly efficient debug environment for MIPS and ARM based SoCs.”
“Codelink has proven to be a highly cost-effective and efficient tool for us, particularly the replay feature,” said Kenneth Bartsch, Verification Lead at InterDigital. “Prior to Codelink, certain bugs required multiple one-day re-simulations to fully diagnose. With Codelink replay we simulate just one time, and isolate the failure (hardware or software) immediately. Both software and hardware engineers like the tool. Codelink was key to us taping out our new SlimChip™ SoC on schedule.”
Pricing and Availability
The Questa Codelink product is available now with a starting price of $28,400. The following families of processors are currently supported: ARM7, ARM9, ARM11, ARM Cortex, MIPS 4, MIPS 24, and MIPS 74.
Questa Functional Verification Platform
The Questa Functional Verification Platform combines high performance and high capacity with the most comprehensive verification capabilities in the industry. Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVC), and Coverage-driven Verification (CDV) are supported natively by the Questa platform’s high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB). Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM) that delivers unrivaled language and feature support in any design and verification flow.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $875 million and employs approximately 4,350 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
|
||||||
Related News
- DMAP Announces Development of DO-254 DAL A Complex Semiconductor IP, Fully Verified with Mentor Graphics Questa® Functional Verification Platform
- Mentor Graphics Transforms SoC Integration and Functional Verification with Next Generation Questa Platform
- Mentor Graphics Questa Functional Verification Platform Selected by Cypress Semiconductor
- New Software for Mentor Graphics Questa Platform Enables Early Verification of IEEE 1149.1-2013 Compliant IP and On-Chip Instruments
- Mentor Graphics Questa Verification Platform Adds Software-Driven Verification for Multi-Core SoC Designs
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
|
E-mail This Article | 
|
|
Printer-Friendly Page |