English
TSMC Unveils New 40/65-Nanometer SPICE Tool Qualification Program
Increases SPICE Modeling Accuracy and Simulation Performance for High Performance Chip Designs
Hsinchu, Taiwan, R.O.C. – April 22, 2008 - Taiwan Semiconductor Manufacturing Company, Ltd. today unveiled at its opening 2008 Technology Symposium a comprehensive SPICE Tool Qualification Program that drives its Design Service ecosystem partners to develop SPICE simulators with greater accuracy and higher performance.
Targeting TSMC’s 65-, 40-nanometer (nm) and smaller geometry process technologies, the program’s benefits include improved device model accuracy, enhanced simulation efficiency, and compatibility across a wide selection of qualified SPICE simulators. The program also improves simulation accuracy, shortens transistor-level simulation cycle time, increases simulation capacity, and ultimately enables faster time-to-market and first time silicon success.
To address emerging nanometer effects associated with the 40nm technology and beyond, the company is introducing iSDK, interoperable SPICE Design Kit, together with the TSMC’s Model Interface (TMI), a new device modeling innovation and simulation performance improvement. Written in standard C language, iSDK with TMI is a new method for compact SPICE device modeling that is an addition to the traditional, and slower macro modeling approach. TSMC will provide iSDK through a common compiled shared library that will link directly to a vendors’ SPICE simulators.
Once the SPICE simulator passes SPICE tool qualification TSMC will post a qualification report on TSMC-Online, the company’s customer only portal. Multiple EDA partners are already participating in the program including Agilent Technologies, Berkeley Design Automation, Cadence, Magma, Mentor, Simucad, and Synopsys.
“TSMC is the first foundry to deliver on the commitment of providing more design accuracy by proactively working with multiple EDA vendors to create and qualify interoperability between SPICE simulation technologies and the foundry’s most advanced processes technologies,” said S.T. Juang, senior director, Design Infrastructure Marketing at TSMC.
“Going beyond the traditional tool qualification program, TSMC’s Modeling Interface architecture sets a new standard in SPICE modeling accuracy and simulation efficiency. The program provides designers the ability to select qualified SPICE simulators to match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first time silicon success,” he explained.
About TSMC Active Accuracy Assurance Initiative
The TSMC AAA initiative is a broad-based program that encompasses all components of the design ecosystem. It provides standards of accuracy to all TSMC partners, including EDA tool suppliers, IP providers, library developers, and Design Center Alliance (DCA) partners. TSMC applies the same standards to tools, building blocks, and technologies, including TSMC Reference Flow 8.0, design for manufacturing (DFM) tools, process design kits (PDK), design support and backend services.
About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2007 exceeded eight million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.
Hsinchu, Taiwan, R.O.C. – April 22, 2008 - Taiwan Semiconductor Manufacturing Company, Ltd. today unveiled at its opening 2008 Technology Symposium a comprehensive SPICE Tool Qualification Program that drives its Design Service ecosystem partners to develop SPICE simulators with greater accuracy and higher performance.
Targeting TSMC’s 65-, 40-nanometer (nm) and smaller geometry process technologies, the program’s benefits include improved device model accuracy, enhanced simulation efficiency, and compatibility across a wide selection of qualified SPICE simulators. The program also improves simulation accuracy, shortens transistor-level simulation cycle time, increases simulation capacity, and ultimately enables faster time-to-market and first time silicon success.
To address emerging nanometer effects associated with the 40nm technology and beyond, the company is introducing iSDK, interoperable SPICE Design Kit, together with the TSMC’s Model Interface (TMI), a new device modeling innovation and simulation performance improvement. Written in standard C language, iSDK with TMI is a new method for compact SPICE device modeling that is an addition to the traditional, and slower macro modeling approach. TSMC will provide iSDK through a common compiled shared library that will link directly to a vendors’ SPICE simulators.
Once the SPICE simulator passes SPICE tool qualification TSMC will post a qualification report on TSMC-Online, the company’s customer only portal. Multiple EDA partners are already participating in the program including Agilent Technologies, Berkeley Design Automation, Cadence, Magma, Mentor, Simucad, and Synopsys.
“TSMC is the first foundry to deliver on the commitment of providing more design accuracy by proactively working with multiple EDA vendors to create and qualify interoperability between SPICE simulation technologies and the foundry’s most advanced processes technologies,” said S.T. Juang, senior director, Design Infrastructure Marketing at TSMC.
“Going beyond the traditional tool qualification program, TSMC’s Modeling Interface architecture sets a new standard in SPICE modeling accuracy and simulation efficiency. The program provides designers the ability to select qualified SPICE simulators to match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first time silicon success,” he explained.
About TSMC Active Accuracy Assurance Initiative
The TSMC AAA initiative is a broad-based program that encompasses all components of the design ecosystem. It provides standards of accuracy to all TSMC partners, including EDA tool suppliers, IP providers, library developers, and Design Center Alliance (DCA) partners. TSMC applies the same standards to tools, building blocks, and technologies, including TSMC Reference Flow 8.0, design for manufacturing (DFM) tools, process design kits (PDK), design support and backend services.
About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2007 exceeded eight million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.
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