Rambus Announces IBM to License Multi-protocol Serdes
Single Low-Power SerDes IP Cell Supports Wide Range of Protocols Spanning 1.25-6.4Gbps
Los Altos, California, United States - April 22, 2008 -- Rambus Inc. (NASDAQ: RMBS), one of the world's premier technology licensing companies specializing in high-speed memory architectures, today announced that IBM has licensed Rambus' multi-protocol SerDes (Serial/Deserializer) cell designed for advanced networking, server and general ASIC applications. This sophisticated multi-protocol SerDes cell provides IBM with a high-performance and low-power solution for implementation on its 45nm silicon-on-insulator (SOI) technology.
"The SerDes requirements for ASICs and servers are increasingly demanding and cover many protocols," said Steve Longoria, vice president for Semiconductor Solutions, IBM. "Rambus' multi-protocol SerDes solution gives us a flexible, single IP solution that simplifies the design process without compromising performance, power or silicon die area."
The Rambus multi-protocol SerDes is a single IP cell leveraging a scalable architecture that offers data rates of 1.25 Gbps to 6.4 Gbps. It features an advanced Rambus phase-locked loop (PLL) architecture, which achieves low jitter over a wide variety of operating data rates and enables best-in-class performance in a small silicon die area.
"Our customers are faced with design challenges that call for both high performance and low power in order to meet their application requirements," said Sharon Holt, senior vice president of Worldwide Sales, Licensing and Marketing at Rambus. "IBM is renowned for its advanced technology, and we are pleased to provide our innovative multi-protocol SerDes for its ASIC library and product offerings."
The Rambus SerDes solution also incorporates the Rambus LabStation™ characterization environment, enabling thorough qualification, advanced testability features, and improved time-to-market.
For more information on Rambus' multi-protocol SerDes solution please visit http://www.rambus.com.
About Rambus Inc.
Rambus is one of the world's premier technology licensing companies specializing in the invention and design of high-speed memory architectures. Since its founding in 1990, the Company's patented innovations, breakthrough technologies and renowned integration expertise have helped industry-leading chip and system companies bring superior products to market. Rambus' technology and products solve customers' most complex chip and system-level interface challenges enabling unprecedented performance in computing, communications and consumer electronics applications. Rambus licenses both its world-class patent portfolio as well as its family of leadership and industry-standard interface products. Headquartered in Los Altos, California, Rambus has regional offices in North Carolina, India, Germany, Japan, Korea and Taiwan. Additional information is available at www.rambus.com.
|
Related News
- Toshiba Adds Multi-Protocol High-Speed SERDES I/O Core Family That Meets High Speed Requirements of Storage, Networking, Consumer and Gaming Markets
- Prism Announces Mindspeed Technologies to License Interconnect IP
- Modelware Announces PluriBus™ iUniversal Bus Interface Core for Multi-rate, Multi-protocol Applications
- Xilinx Virtex-II Platform FPGAs Validate World's First 10 Gb/s Multi-Protocol Module From Network Elements
- Rambus and Phison Sign Patent License
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |