Improv rolls reconfigurable processors

Improv rolls reconfigurable processors
By Will Wade, EE Times
March 6, 2000 (3:05 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000306S0083

SAN MATEO, Calif. — Startup Improv Systems Inc. has delivered test chips of its reconfigurable processors and announced the devices' first customer. Improv plans to market its flexible cores to ASIC vendors and semiconductor companies and is focused primarily on the communications sector.

Cary Ussery, president, chief executive officer and founder of Improv (Beverly, Mass.), said reconfigurable chips are starting where the core-based intellectual-property (IP) segment has floundered. "The core-based approach is not working," he said, because the sheer volume of different architectures has made it nearly impossible to create a robust design without encountering significant bugs as the cores attempt to communicate with each other. Legal issues over ownership and payment have also contributed to the segment's problems, he said.

"We started with the idea that rather than requiring people to roll their own ICs, it's better to come up with a chip that's completely software-programmable," Ussery said.

The Improv architecture is centered on the company's VLIW Jazz processor core. Each core has 32 kbits to 64 kbits of internal memory, and the chips are designed so an additional pair of memory blocks outside the cores are shared by every three processors. The Jazz core processes 12 to 14 operations per instruction, so a single Jazz running at 100 MHz can deliver up to 14 billion operations per second of processing power, Ussery said.

The first company to publicly announce an Improv-based design is Philips Semiconductors, which will be producing a five-processor chip for the communications segment. Other deals are in place or are close to completion, according to Improv.

Ussery said Improv will follow a "chipless" business model, and plans to license its technology to chip makers for an up-front fee and a back-end, per-chip royalty.

Although Ussery said there is no physical limit to the amount of processors that could be implemented on a single die, he expects most designs initially to use three to four of the Jazz cores. He said the main market for the technology is network processors for standard routing and switching as well as more specialized devices for the burgeoning packetized voice and multimedia application markets.

The Improv architecture can be modified at both the chip level, by changing the number of processors and the various I/O formats, and on the core level by modifying the size of the chip's memory and data paths.