Synopsys' New Highest-Performance VHDL Simulator Expands Support for System Design and Verification

MOUNTAIN VIEW, Calif.----March 6, 2000-- Synopsys, Inc. (Nasdaq: SNPS) the technology leader for complex integrated circuit (IC) design, today extended its system design and verification solution with the announcement of the Scirocco(TM) VHDL simulator. Scirocco's revolutionary new technology unites the dramatic performance potential of cycle technology with the flexibility of event-driven simulation. The technology breakthrough delivers the highest-performance and largest capacity available in any VHDL simulator, allowing rapid and thorough verification of complex system-on-a-chip (SoC) designs.

Advance access to Scirocco provided design teams from a number of customers, including Fujitsu Tohoku Digital Technology, Mitel and Xerox Corporation, with a typical 5X performance acceleration compared to other VHDL simulators. Simulation run time performance gains of more than 20X have been achieved for designs containing mostly synchronous, synthesizable RTL.

``Synopsys continues to focus its R&D on innovative solutions to our customers' three toughest SoC design challenges: system-level design and verification, timing closure and IP reuse,'' noted Dr. Aart de Geus, chairman and CEO of Synopsys. ``The increasing complexity of today's chip designs brings an explosion of the verification problem. Our new Scirocco simulator is a key technology that will help customers solve this problem and get their products to market faster.''

``With Scirocco, we were able to run a system simulation of our one-million gate plus SoC with its associated testbenches and IP models in one day. This same simulation previously required a week,'' said Samuel Ambalavanar, Advanced ASIC project manager for Xerox Corporation. ``This significantly improved our simulation coverage and regression testing, allowing us to test more of our system than would have been possible with our existing event-driven VHDL simulator. For example, we used Scirocco to simulate one of the modules in our SoC where it delivered an impressive 22X speed improvement.''

Scirocco applies Synopsys' market-proven cycle-based optimization techniques for synthesis-based RTL designs while supporting the full VHDL93 language for testbenches, behavioral models and legacy gate-level designs. It delivers cycle-based simulation performance without the language and design style restrictions typically required by cycle-based simulators.

``We are very impressed with how Scirocco was able to outperform our current simulators by 8X,'' said Kazuhiro Suzuki, project manager, Fujitsu Tohoku Digital Technology Limited, a leader in telecommunications. ``We were able to drop our design into Scirocco without having to modify the design or the testbench. This was a big benefit to us since we were able to realize significant performance gains with very little effort.''

Complete Verification Environment Including High-Performance
Mixed-Language Support

Scirocco's advanced performance-optimized architecture is based on a unified simulation kernel that combines event, cycle and mixed-language techniques to offer designers working in VHDL a level of performance already familiar to users of Synopsys' industry-leading VCS(TM) Verilog simulator. Scirocco leverages VCS to enable integration of Verilog intellectual property without sacrificing performance. It provides this capability without requiring the design team to learn the nuances of the Verilog language or become familiar with a separate mixed-language simulator.

The Scirocco simulator forms the basis of a complete verification environment that can include application-specific tools from both Synopsys and third-party tool providers. It is the first simulator to fully support the open-standard VHPI interface.

Scirocco is tightly integrated with Synopsys' suite of advanced verification products including: the VERA(TM) testbench automation and analysis system; the Synopsys Eaglei® hardware/software co-verification tools; Logic Modeling® simulation models and Synopsys' system-level design environment.

In addition, Scirocco offers superior integration through VHPI to third-party tools including those from Aptix, Chronology, Denali, IKOS, Novas, Summit and TransEDA.

Advanced User Interface Provides Robust Debug and Analysis

As design complexity increases, customers are reporting that the task of managing simulation results has become extremely difficult. Scirocco's VirSim(TM) graphical user interface (GUI) from Summit Design Automation provides the fastest and easiest way to debug and analyze massive quantities of simulation data and rapidly pinpoint design errors.

The VirSim interface provides VHDL designers with unique interactive and post-simulation analysis capabilities. Multiple graphical windows display simulation waveform data, offer source-level language debug and innovative register display.

Pricing and Availability

Synopsys' Scirocco is available today. A variety of configurations are available, with pricing starting at US $15,000 on Sun Solaris and Hewlett-Packard HP-UX workstations. For more information on Scirocco or other Synopsys verification tools, contact your local Synopsys sales representative, visit the worldwide web at: www.synopsys.com/verifyit, email verify@synopsys.com, or, in North America, call 1-800-346-6335.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS), is a leading supplier of electronic design automation (EDA) solutions to the global electronics market. The company provides comprehensive design technologies to creators of advanced integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting services and support to its customers to streamline the overall design process and accelerate time-to-market. Additional information about Synopsys is available at www.synopsys.com.

Synopsys, Logic Modeling and Synopsys Eaglei are registered trademarks and VCS, VERA and Scirocco are trademarks of Synopsys, Inc. VirSim is a trademark of Summit Design. All other trademarks mentioned in this release are the intellectual property of their respective owners.

Contact:
     Synopsys, Inc.
     Diane Landers
     503-748-2252
     dianel@synopsys.com
     or
     KVO Public Relations
     LeAnne Frank
     503-221-7403
     leanne_frank@KVO.com