Process Detector (For DVFS and monitoring process variation)
Iveia Announces the Titan-V5e Small Form Factor Processing Module Utilizing System-On-A-Chip Technology and the Xilinx Virtex- 5 FXT
ANNAPOLIS, MD -- May 5, 2008 -- iVeia, LLC today announced the availability of the Titan-V5e, a small form factor processing module that utilizes the newly released Virtex-5 FXT FPGA from Xilinx. The Titan-V5e combines the embedded PowerPC 440 processor of the Virtex-5 FXT with iVeia’s Velocity-SoC technology, enabling the rapid development of high-performance signal and image processing applications in an ultra-small form factor.
The Titan-V5e is the latest addition to iVeia's Titan family of credit card size COTS processing modules. The new module packs a Virtex-5 FX70T FPGA with a 1000+ DMIPs hardened PowerPC processor, three configurable banks of DDR2 SDRAM, two Gigabit Ethernet interfaces, up to 32GB of on-board FLASH, a flexible I/O interface, and a scalable backplane interface. Virtex-5 SXT configurations are also available.
The unique System-on-a-Chip (SoC) architecture provides the compute power of both an advanced microprocessor and a state-of-the-art FPGA. “More and more compute-intensive signal and image processing applications are migrating to FPGA-microprocessor hybrid architectures” explains Michael Fawcett, CTO of iVeia. “The advances in the Virtex-5 FXT FPGA enabled iVeia to create a hybrid architecture on a single chip, thereby improving performance and flexibility while reducing size, power, and cost. This makes the Titan-V5e ideal for man-portable applications, robotics and machine vision, unmanned vehicles, smart cameras, and an abundance of other commercial and military applications.”
Industry-specific development kits are available for the Titan-V5e that provide a complete path from development to deployment. Each kit includes iVeia's Velocity-SoC IP core and SDK, an optimized framework and abstraction layer that decouples the FPGA and software design allowing for rapid application development.
iVeia offers a variety of GigaFlex I/O modules for the Titan-V5e. For a complete list and for custom configurations contact iVeia or visit www.iVeia.com.
About iVeia, LLC
Founded in 2005, iVeia is a veteran-owned small business focused on providing high-performance, low-cost solutions where size, weight, and power are critical requirements. iVeia’s scalable and modular architectures allow for rapid development of cost-effective signal and image processing systems.
|
Related News
- Xilinx Introduces New Development Kit for Building High-Performance Embedded Processing Systems with Virtex-5 FXT FPGAs
- Xilinx Ships Virtex-5 FXT FPGAs, Delivering the Ultimate in System Integration for Designs That Demand High-Performance Processing and High-Speed Serial I/O
- Xilinx Ships First Artix-7 FPGAs - Raising the Performance Bar for Portable and Small Form Factor Applications at the 'Edge'
- PLDA announces immediate availability of PCIe 2.0 IP Core supporting new Xilinx Virtex-5 FXT FPGAs
- Xilinx Delivers 50% Lower System Cost With New Small Form Factor FPGAs
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |