MoSys, Virage develop next-generation memory compilers for TSMC processes

MoSys, Virage develop next-generation memory compilers for TSMC processes
By Semiconductor Business News
February 29, 2000 (9:34 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000229S0004

SUNNYVALE, Calif. -- MoSys Inc. here and nearby Virage Logic Corp. today announced a partnership to develop fourth-generation memory compilers for 0.18- and 0.15-micron logic processes offered by Taiwan Semiconductor Manufacturing Co. Ltd.

The new memory compilers will be based on MoSys' single-transistor SRAM technology--called 1T-SRAM--and Virage's Custom-Touch compiler. The goal is to create compilers for extremely high-density memory blocks that are embedded in system-on-chip designs for TSMC's new standard logic processes. The compilers will employ "what-if-analysis" and performance trade-off capabilities early in the design cycle to help speed SoC development, said the two Silicon Valley partners.

"Custom-Touch 1T-SRAM compilers for our leading 0.15- and 0.18-micron processes gives customers easy access to high capacity memory required in these designs," Roger Fisher, senior director and corporate marketing at TSMC. The first Custom-T ouch 1T-SRAM compiler is scheduled to become available in the second quarter of 2000.

"The MoSys-Virage partnership is committed to proliferating this unique memory technology to enhance productivity and enable system designers to make smart technical decisions without making any unnecessary compromises," said Vin Ratford, vice president of marketing and sales at Virage, based in Fremont, Calif. "For the first time the performance benefits of SRAM and density advantages of DRAM can be combined in a compilable form."