English
EVE to Showcase Transaction-Level Modeling Capabilities During DAC
SANTA CLARA, Calif. -- May 20, 2008 -- EVE, the leader in hardware/software co-verification, will showcase an expanded library of standard transactors and a new custom transactor development tool during the 45th Design Automation Conference (DAC) in booth #301 June 9-12 at the Anaheim Convention Center in Anaheim, Calif.
EVE is adding two new transactors to its extensive library of the most common standard protocols, an AXI Master/Slave transactor and a PCIe Gen 2.0 16x transactor. Both can be connected easily to the design, reducing the setup time for the testbench by eliminating the need for hardware speed bridges or synthesizable testbenches. They offer a high-level application programming interface (API) enabling the designer to quickly create application-oriented test sequences.
In an effort to simplify the creation of transactors for custom protocols and to raise the level of abstraction for hardware debugging, EVE also unveiled ZEMI-3, a new transaction modeling methodology to quickly and easily create custom transactors.
Fully backward compatible with SystemVerilog, ZEMI-3 code works in either emulation or in simulation in the same way, without the need for libraries or conversions.
“ZEMI-3 is a key component of our hardware debugging offering,” states Dr. Luc Burgun, EVE’s chief executive officer and president. “It enables designers to put in place a transaction-level monitoring methodology for debugging hardware design, reducing the time spent analyzing waveforms. ZEMI-3 is a significant improvement in the way transactors are written transactors for custom protocols, leading to fast turnaround time and improved productivity for design teams adopting a transaction-based verification approach.”
With ZEMI-3, it is easy to develop bus functional models (BFMs) because of its embedded behavioral compiler. Clocks between emulated designs under test (DUTs) and the testbench are automatically synchronized when needed, and only when needed. It automatically streams data when possible, making sure the data is moved to its destination before it’s needed.
Other solutions synchronize every event between testbench and emulation so that the testbench and emulation run cycle by cycle, defeating the purpose and benefits of transaction-level modeling. Because ZEMI-3 uses a functional programming paradigm, the transaction is the function call, an intuitive and transparent feature for verification engineers because they do not have to consider the channel of communication.
Says Lauro Rizzatti, vice-president of marketing and EVE-USA general manager: “Transaction-level methodology moves design teams away from in-circuit emulation and synthesizable testbenches. It offers a way to validate software in SoC designs faster –– at megahertz instead of kilohertz speed –– while accelerating the hardware debugging process.”
Pricing and Availability
ZEMI-3 is available now. It is priced at $80,000.
AXI and PCIe Gen 2.0 transactors are available now and are priced from $15,000.
For more information, contact Lauro Rizzatti, general manager of EVE USA and vice president of worldwide marketing. He can be reached at (408) 855-3201 or via email at lauro@eve-team.com. More details about ZEMI-3 can be found at the EVE website located at: http://www.eve-team.com.
About EVE
EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its United States headquarters are in Santa Clara, Calif. Telephone: (408) 855-3200. Facsimile: (408) 845-9209. Corporate headquarters are in Palaiseau, France. Telephone: (33) 1 64.53.27.30. Fax: (33) 1 64.53.27.40. Email: info@eve-team.com. Website: http://www.eve-team.com.
EVE is adding two new transactors to its extensive library of the most common standard protocols, an AXI Master/Slave transactor and a PCIe Gen 2.0 16x transactor. Both can be connected easily to the design, reducing the setup time for the testbench by eliminating the need for hardware speed bridges or synthesizable testbenches. They offer a high-level application programming interface (API) enabling the designer to quickly create application-oriented test sequences.
In an effort to simplify the creation of transactors for custom protocols and to raise the level of abstraction for hardware debugging, EVE also unveiled ZEMI-3, a new transaction modeling methodology to quickly and easily create custom transactors.
Fully backward compatible with SystemVerilog, ZEMI-3 code works in either emulation or in simulation in the same way, without the need for libraries or conversions.
“ZEMI-3 is a key component of our hardware debugging offering,” states Dr. Luc Burgun, EVE’s chief executive officer and president. “It enables designers to put in place a transaction-level monitoring methodology for debugging hardware design, reducing the time spent analyzing waveforms. ZEMI-3 is a significant improvement in the way transactors are written transactors for custom protocols, leading to fast turnaround time and improved productivity for design teams adopting a transaction-based verification approach.”
With ZEMI-3, it is easy to develop bus functional models (BFMs) because of its embedded behavioral compiler. Clocks between emulated designs under test (DUTs) and the testbench are automatically synchronized when needed, and only when needed. It automatically streams data when possible, making sure the data is moved to its destination before it’s needed.
Other solutions synchronize every event between testbench and emulation so that the testbench and emulation run cycle by cycle, defeating the purpose and benefits of transaction-level modeling. Because ZEMI-3 uses a functional programming paradigm, the transaction is the function call, an intuitive and transparent feature for verification engineers because they do not have to consider the channel of communication.
Says Lauro Rizzatti, vice-president of marketing and EVE-USA general manager: “Transaction-level methodology moves design teams away from in-circuit emulation and synthesizable testbenches. It offers a way to validate software in SoC designs faster –– at megahertz instead of kilohertz speed –– while accelerating the hardware debugging process.”
Pricing and Availability
ZEMI-3 is available now. It is priced at $80,000.
AXI and PCIe Gen 2.0 transactors are available now and are priced from $15,000.
For more information, contact Lauro Rizzatti, general manager of EVE USA and vice president of worldwide marketing. He can be reached at (408) 855-3201 or via email at lauro@eve-team.com. More details about ZEMI-3 can be found at the EVE website located at: http://www.eve-team.com.
About EVE
EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its United States headquarters are in Santa Clara, Calif. Telephone: (408) 855-3200. Facsimile: (408) 845-9209. Corporate headquarters are in Palaiseau, France. Telephone: (33) 1 64.53.27.30. Fax: (33) 1 64.53.27.40. Email: info@eve-team.com. Website: http://www.eve-team.com.
|
||||||
Related News
- Open SystemC Initiative Announces Proposal for Significant Extensions to Transaction-Level Modeling (TLM) Standard
- The Open SystemC Initiative Announces Availability of the SystemC Transaction-level Modeling Standard with Broad Industry Support
- Konica Minolta Accelerates Hardware Debugging with EVE's ZEMI-3 Transaction-Level Modeling Methodology
- Open SystemC Initiative Announces Completion of New Standard Enabling the Real-World Interoperability of Transaction-Level Models
- Novas, Denali Offer First Transaction-Level Verification and Debugging Environment for PCI Express Design Verification
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |