eASIC zooms past 100th
90nm ASIC design win in 18 months
Santa Clara, CA – June 2, 2008 – eASIC Corporation, a provider of zero mask-charge ASIC devices, today announced that it has surpassed 100 design wins in only 18 months for it’s Nextreme family of 90nm ASIC devices. These design wins demonstrate rapid adoption into both mature and emerging markets including digital consumer, telecommunication infrastructure, wireless, medical, video surveillance and broadcast. eASIC's Nextreme family of zero mask-charge and no minimum order ASIC devices, combines the low cost benefits of traditional ASIC devices with a rapid design cycle and only a four week silicon turnaround time.
“eASIC’s Nextreme devices offered us the only solution to meet the stringent cost, performance and power requirements for our consumer digital video products,” said Sunny Ng, Vice President of Engineering at Aurora Systems. “We were extremely impressed with the fast turnaround time and low up front cost. I am not surprised that eASIC has rapidly reached this impressive milestone. We are privileged to be the recipient of the 100th Design Win award.”
Traditional ASIC technologies have suffered a dramatic decrease in design starts over the past ten years. From over 10,000 annual designs a decade ago, traditional ASICs now claim less than 4,000 designs annually. Industry analysts expect multi-million dollar NRE charges for traditional ASICs to continue to erode this segment of the market.
“The cost of traditional ASIC customization became prohibitive for the majority of applications and designers. eASIC’s zero mask-charge Nextreme devices have changed that landscape,” said Ronnie Vasishta, President and CEO of eASIC. “This milestone demonstrates that customers have embraced Nextreme ASIC as the vehicle for affordable silicon customization. Our wide variety of customers include fabless semiconductor companies, IDMs and system OEMs. 30 percent of these design wins are from multinational, publicly traded companies.”
About eASIC
eASIC is a fabless semiconductor company offering breakthrough zero mask-charge ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer ASICs with no mask-charges and no minimum order quantity,
Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information, please visit www.eASIC.com
|
Related News
- eASIC Delivers 45nm Zero Mask-Charge New ASIC Family
- eASIC and Tensilica Partnership Delivers Free Diamond Processors on Free Mask Charge ASICs
- eASIC and GenCore Form Partnership for Distribution of Nextreme Structured ASIC Devices in Korea
- Zero ASIC Democratizing Chip Making
- EnSilica evaluation platform for EN62020 sensor interface ASIC speeds up development of wearable fitness and healthcare sensor devices
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |