Design Art Networks selects TurboConcept FEC solutions
Brest, France -- July 15, 2008 -- TurboConcept announced today that DesignArt Networks has successfully incorporated TC1000-WiMAX turbo encoder/decoder solutions into its 4G Silicon Platform SoC.
“The TC1000-WiMAX Core is a powerful, low-complexity and flexible core, allowing us to reach the high-speed turbo encoding and decoding performance that we needed for WiMAX access and simultaneous high-capacity in-band backhaul, based on reduced die size and power consumption. We look back to a very effective integration phase, together with TurboConcept’s high-calibre engineering and support team, helping us to choose the best parameters to operate the cores according to target within the constraints of a very high performance architecture.” said Assaf Touboul, co-founder and CTO, Design Art Networks.
“It is important for our customers to concentrate on their key technology and positioning, and have the highest trust on the performance and reliability when they outsource an IP Core. By providing Design Art with our optimized turbo encoder and decoder engines, we are proud to contribute to their unique positioning in the WiMAX radio access and backhaul infrastructure”, said Jacky Tousch, co-founder & CTO, TurboConcept.
TC1000-WiMAX turbo encoder and decoder Cores are compliant with WiMAX fixed and mobile profiles. The cores fit in low complexity budgets and have built-in features for reduction of power consumption. Over 200 Mbits/s payload can be reached by a single core instance. The core is flexible and offers adaptive trade-offs between performance, throughput, functionality and device footprint.
The TC1000-WiMAX Core is a robust and proven solution, adopted by a large community of base station and mobile station manufacturers, serving in FPGA, ASIC and SoC architectures.
About TurboConcept
TurboConcept is a leading provider of Intellectual Property Cores for advanced FEC (Forward Error Correction) techniques – Turbo and LDPC codes. TurboConcept has a large portfolio of Cores covering Convolutional Turbo Codes, Turbo Product Codes and LDPC codes, addressing open specifications (e.g. 3GPP-LTE, DVB-S2, WiMAX, HomePlug, CCSDS, DVB-RCS) or optimized proprietary schemes. The Cores are offered as RTL source code (Verilog or VHDL) for ASIC implementation, and as synthesized netlist for Altera, Xilinx and Lattice FPGA devices. www.turboconcept.com
About Design Art
DesignArt Networks LTD is the leading supplier of system-on-chip (SoC) solutions driving the evolution of the 4G radio network infrastructure, towards high-capacity, high-density deployments with ubiquitous outdoor and indoor coverage. Current DesignArt products are based on the mobile WiMAX standard, IEEE 802.16e-2005, offering single-chip solutions for any type and form factor of base or relay station. DesignArt is the first and only WiMAX silicon vendor to fully integrate all base station processing systems in a single-chip SoC architecture, enhanced with high-capacity backhaul, relay and cluster capabilities,. DesignArt offers the most compact and powerful design options to equipment manufacturers, enabling them to build the widest range of WiMAX femto, pico, micro and multi-sector base stations, including multi-media relay and WiMAX cluster solutions. Zero-cost in-band backhaul solutions drastically lower the total cost of ownership (TCO) for operators, and are the catalyst to accelerated WiMAX and 4G deployments. www.designartnetworks.com
|
Related News
- TurboConcept's TC1000WiMAX turbo decoder Core incorporated in Sequans' WiMAX chips
- Reed Solomon Encoder and Decoder FEC IP Core From Global IP Core
- NR-5G Polar Decoder and Encoder FEC IP Core Available For Licensing and Implementation from Global IP Core
- DVB-RCS2 Turbo Decoder and Encoder IP Core Available For Integration From Global IP Core
- CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |