eInfochips announces MIPI SystemVerilog Verification IP
MIPI (Mobile Industry Processor Interface) VIP is a SystemVerilog component compliant to CSI-2 MIPI specification for Camera Serial Interface Version 1.00 and DRAFT MIPI Alliance Standard for D-PHY Version 0.85.00.
Ahmedabad, India. -- August 4, 2008 -- eInfochips, Inc., a leading IP leveraged design services company today announced the availability of CSI-2 (Camera Serial Interface Version 1.00) & D-PHY 0.85.00 compliant MIPI SystemVerilog verification component.
eInfochips’ SystemVerilog MIPI verification component is based on a layered object oriented architecture that allows coverage driven system level verification suitable for verification of MIPI transmitter or receiver DUT (Design Under Test).
MIPI VIP
The MIPI (Mobile Industry Processor Interface) SystemVerilog VIP generates High Speed, Escape-LPDT, Escape-ULPS and Escape Trigger modes of data traffic with various formats on virtual channels for multiple data lanes. It has support for error injections and detections for ECC, Synchronization, CRC, Payload and Unrecognized ID detection with an FSM based protocol checker. MIPI Monitor uses SystemVerilog assertion to check for timing violations, if any, at the DPHY interface. Functional coverage mechanism helps determine uncovered configuration variables. MIPI VIP is highly configurable for primary images data formats, number of images (maximum 4), number of lines in the image, number of data-lanes and interleaved image transfers.
Availability & Deliverables
Deliverables include completely verified verification component encrypted code, user guide, release notes and sample test cases. eInfochips' IP support staff meet customer requirements related to integrating IP into test environment and other support related issues. For pricing details write to us at sales@einfochips.com.
For more information on the IPs please visit: http://www.einfochips.com/ips/MIPI_VIP.html (MIPI VIP)
About eInfochips
eInfochips is a leading provider of ASIC/SoC design & verification services, embedded system solutions, IP cores and software product development solutions & services. eInfochips has contributed to over 150 chip designs in automotive, consumer, semiconductor, avionics, networking and communication segments through its wide array of RTL to GDS II services and solutions. The company's design centers have delivered SoC and embedded solutions to a variety of customers thus increasing cost-effectiveness, reducing time-to-market and growing their market strength.
|
Related News
- eInfochips Announces VMM-Enabled MIPI CSI-2, DSI & HSI and SDIO Verification IP for the Synopsys DesignWare Verification IP Alliance Program
- eInfochips announces AVM 3.0 & OVM Compliant SystemVerilog AMBA AHB Verification IP
- eInfochips Supports the Mentor Graphics' Questa(TM) Vanguard Program for AMBA AHB SystemVerilog Verification Component
- eInfochips Offers SystemVerilog Migration Services from Legacy Verification Environments
- Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |