User Advisory Group Established to Guide Evolution of the Open Verification Methodology
SAN JOSE, Calif., & WILSONVILLE, Ore. -- August 06, 2008 -- The Open Verification Methodology (OVM) World community today announced the OVM Advisory Group (OAG), an organization of distinguished users and ecosystem suppliers, is helping to develop new features and capabilities for the OVM. Founding members of the OAG include ARM; Cisco Systems, Inc.; Denali Software, Inc.; Freescale Semiconductor, Inc.; IBM Corp.; Infineon Technologies; Nokia Corp.; STMicroelectronics NV and Xilinx, Inc.
“The OVM is available under the Apache 2.0 open-source license, so our OVM-based verification environments are usable with all commercial simulators supporting the SystemVerilog testbench subset,” said Jean-Marc Chateau, group vice president, IP & Design, at STMicroelectronics. “One of our main interests in participating in the OAG is to drive the evolution of the OVM according to our needs by providing our feedback and requirements to the group.”
Input from the user community and members of the OAG, which first met in February 2008, is reflected in the latest release of the OVM, version 1.1, now available for download from OVM World at www.ovmworld.org. This release includes enhancements to stimulus generation arising directly from user experiences. With more than 4,400 registered users and hundreds of industry projects using the OVM, the OAG already has a wealth of suggestions and proposals to consider for future releases.
About Open Verification Methodology
The Open Verification Methodology, based on IEEE Std. 1800™-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. The OVM and OVM World began in August 2007 as a joint effort by Cadence Design Systems and Mentor Graphics.
|
Related News
- Cadence and Mentor Enhance Open Verification Methodology and Expand Community Activities to Support Rapidly Growing User Base
- Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM
- Paradigm Works Releases Key Verification Productivity Software for the Open Verification Methodology (OVM)
- Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support
- Mentor Graphics Supports Fujitsu to Implement Open Verification Methodology (OVM)
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |