Mentor Graphics Seamless Co-Verification Environment First to Support Infineon Technologies TriCore 32-Bit Unified Processor for Embedded Systems
Mentor Graphics Seamless Co-Verification Environment First to Support Infineon Technologies TriCore 32-Bit Unified Processor for Embedded Systems
WILSONVILLE, Ore., Jan. 18 -- Mentor Graphics® Corp. (Nasdaq: MENT) today announced that it will be the first provider of co-verification support for the TriCore(TM) Unified Processor from Infineon Technologies, an advanced 32-bit architecture for embedded systems.
Under the terms of an agreement, Mentor Graphics will deliver a Seamless® Co-Verification Environment(TM) (CVE(TM)) processor support package (PSP) for the TriCore Unified Processor, based upon technology licensed from Infineon. The Seamless PSP for TriCore provides embedded system designers with the ability to co-verify any system-on-chip or system-on-board that embeds the TriCore Unified Processor.
Mentor Graphics Seamless CVE allows design teams to perform co-verification before creating a physical prototype, enabling early detection and correction of errors in the hardware/software interface. Seamless CVE shortens the development time for embedded systems, such as system-on-chip and system-on-board, reduces the number of hardware prototype iterations and accelerates the debug of all levels of software developed for the target system.
``New systems that require previously unattainable levels of integration are likely candidates for IC designs based on the TriCore architecture and co-verified by Mentor Graphics Seamless CVE,'' said Steve Neill, Vice President of Core Services for Infineon Technologies. ``Infineon is pleased to be partnering with Mentor Graphics Seamless CVE to provide our customers with a superb, integrated co-verification platform for the TriCore Unified Processor.''
The TriCore Unified Processor architecture utilizes on-chip memory and nanosecond context switching to support real-time control and digital signal processing (DSP) tasks in a single core. It is the first 32-bit RISC architecture to provide concurrent processing of both control and DSP functions, with C and C++ access to DSP functions and the real-time performance required for embedded systems.
``Mentor and Infineon have collaborated very closely to ensure early model availability and high-quality models for design and co-verification of TriCore architecture products,'' said Serge Leef, director of the SoC Verification division. ``By being first-to-market with a co-verification platform for Infineon's TriCore Unified Processor, Mentor further confirms its position as market leader in hardware/software co-verification for embedded systems.''
Mentor will develop and deliver a Seamless PSP for TriCore Unified Processor designs, incorporating the Infineon cycle-accurate Instruction Set Simulator Model, TSIM+, already available to developers writing code for the TriCore architecture. The PSP includes integration with high-level debuggers supported by the TriCore Unified Processor development tool chain, including the Mentor XRAY® Debugger.
Availability
Production shipments of Mentor Graphics' Seamless CVE 4.0 for the TriCore architecture will start in the first quarter of 2000 running on HP and Sun workstations. Pricing of the Seamless PSP for the Infineon TriCore Unified Processor is listed at $30,000. For more information, or to register for a free Seamless workshop, visit Mentor Graphics' Web site at www.mentor.com/seamless.
About Mentor Graphics Seamless CVE
Seamless (CVE) is the industry leader in the global co-verification market with a sixty-two percent market share, according to the most recent study released by Dataquest, Inc. the leading source for Electronic Design Automation (EDA) market intelligence. Combining the best in embedded software development tools with logic simulation, Mentor Graphics Seamless Co-Verification Environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be parallel activities, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.
About Infineon
Infineon Technologies (formerly Siemens Semiconductor Group), based in Munich, Germany, was ranked by Dataquest as the 10th largest semiconductor manufacturer worldwide in 1998. Infineon provides semiconductor solutions for the telecommunications, automotive, data networking, consumer electronics, and industrial automation markets. The company's comprehensive product portfolio includes integrated system ICs, memory and high frequency components, smart card ICs, discrete semiconductors and power ICs, sensors and fiber optic components. In fiscal 1997/98, the company achieved sales of $3.8 billion (DM 6.7 billion) and employed 25,000 people worldwide. Further information is available at http://www.infineon.com .
Infineon Technologies North America Corp. is the company's North American subsidiary, with headquarters at 1730 North First Street, San Jose, CA 95112. For more information, contact 888-463-4636; 408-501-6000.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $500 million and employs approximately 2,600 people worldwide. Company headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com .
NOTE: Mentor Graphics and XRAY Seamless are registered trademarks. Co-Verification Environment and Seamless CVE are trademarks of Mentor Graphics Corporation. TriCore and TSIM+ are trademarks of Infineon Technologies. All other company or product names are the registered trademarks or trademarks of their respective owners.
CONTACT: Anne Cirkel, Public Relations of Mentor Graphics Corp, 503-685-7934, or Anne_Cirkel@mentor.com; or Jeremiah L. Glodoveza of Benjamin Group/BSMG Worldwide, 408-559-6090, or jeremiah_glodoveza@benjamingroup.com, for Mentor Graphics Corp; or Jacob Rice, Public Relations Manager of Infineon Technologies, 408-501-6390, or jacob.rice@infineon.com.
Related News
- Mentor Graphics First to Provide Co-Verification Support for MIPS32 34K Multi-Threading Processor Cores
- Mentor Graphics Delivers Seamless 4.2 Co-verification Environment <!-- verification -->
- Mentor Graphics Enables Hardware/Software Co-Verification with StarCore Processor Models
- MIPS Technologies 24K High-Performance Product Line Supported by Mentor Graphics Seamless Co-Verification Tools
- Infineon Announces Linux Capable 32-bit Microcontroller; Expands TriCore Processor Family with Chip for Industrial and Communications Applications
Breaking News
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PiMCHIP Deploys Ceva Sensor Hub DSP in New Edge AI SoC
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
Most Popular
- DENSO and U.S. Startup Quadric Sign Development License Agreement for AI Semiconductor (NPU)
- Xiphera and Crypto Quantique Announce Partnership for Quantum-Resilient Hardware Trust Engines
- Arm's power play will backfire
- Alchip Announces Successful 2nm Test Chip Tapeout
- Faraday Unveils HiSpeedKit™-HS Platform for High-speed Interface IP Verification in SoCs
E-mail This Article | Printer-Friendly Page |