Evatronix enhances its NAND Flash Controller with OCP interface and BCH error correction code

Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)

Support for Open Core Protocol and Bose, Chaudhuri, and Hocquenghem algorithm increase the controller’s versatility and effectiveness.

Gliwice & Bielsko-Biala, Poland, September 1st, 2008 – The Silicon Intellectual Property (IP) provider, Evatronix SA, announced today the latest upgrade to its highly successful NAND Flash Controller IP core. Both BCH algorithm and OCP socket further facilitate the component’s implementation in various System-on-Chip (SoC) environments, as well as significantly reduce the IP core’s gate count while retaining its outstanding performance.

Bose, Chaudhuri, and Hocquenghem (BCH) algorithm introduces bit-level error correction for Multi Level Cell (MLC) memories, which is a significant performance improvement over Reed-Solomon code’s whole word approach. Furthermore, BCH is designed to handle random scattering of errors - a typical NAND Flash feature. Due to this application-specific character, the algorithm is best suited for the newest types of memories.

Now that more and more popular Open Core Protocol (OCP) became a standard in Evatronix NAND Flash Controller’s interface, SoC designers may take full advantage of the IP core’s advanced features regardless of system bus architecture. OCP socket’s isolation from bus specific decode/selection logic facilitates IP reuse by simplifying the core’s connection to both renowned bus standards (AMBA, Avalon, OPB, VCI, etc.) and individual user’s interfaces for a significant reduction of time-to-market and development costs.

The newest release of the Evatronix NAND Flash Controller leverages many features proven in previous versions, like support for MLC memories with 4 KB page size and up to 128 Gb of capacity. ONFi standard compliance guarantees seamless operation of the NAND Flash Controller with a variety of memories from diverse vendors, while a set of configurable features enables an application-tailored implementation.

“OCP’s versatility makes our IP core independent of system bus architecture,” said Arkadiusz Buchalik, Product Line Manager at Evatronix.“Therefore customers can easily integrate the core not only in current designs, but also in future ones that may use different system buses. This is especially beneficial in multi-use licensing.”

“We can see NAND Flash memories dominating the memory market. With the latest improvements, NAND Flash solutions may be applied in areas that have been unavailable for them for different reasons,” said Wojciech Sakowski,Evatronix President.“By implementing BCH error correction algorithm and OCP support we prove our continuous effort to provide SoC designers with most comprehensive and up-to-date products.”

A complementary software driver that supports the newest features has also been developed. Its operating system independence and support for all necessary NAND Flash memory operation functions make target application development a straightforward task.

Availability and customization options

Both the new version of the NAND Flash Controller IP core and the accompanying driver are available for licensing now. While most of the controller’s features may be configured through a user-friendly IP core configurator, Evatronix engineering team is ready to assist a customer in developing application-specific implementation. The list of potential tasks includes not only direct modifications to the RTL code of the controller, but also development of NAND Flash Controller’s environment elements, like a dedicated system bus wrapper.