Sonics Joins Power Forward Initiative
Currently, advanced SoCs targeting both wireless and wireline applications are experiencing power challenges that require power management solutions spanning the full range from system and architectural design through logical and physical implementation. Coordination among these solutions and across the functional subsystems on the SoC is needed to deliver the required power savings. For this reason, linking architectural power management with implementation-level power management is becoming an important requirement to realize overall power savings.
“Sonics has a vision of enabling designers to efficiently manage power consumption by seamlessly linking power domain architectures and the associated controllers to the physical implementation domain,” said Benoit de Lescure, application engineer and power management expert, Sonics Inc. “We have adopted the Common Power Format (CPF) as a mechanism to connect our architecture-level, low-power initiative with the chip design and manufacturing solutions from Cadence. By combining power-sensitive interconnects with power-aware design verification and implementation methodology, SoC developers can expect seamless power management through the entire process from architecture concept to silicon.”
Sonics SMART Interconnect solutions combine aggressive fine grain clock gating to minimize active power with coarse grain gating to minimize idle power, resulting in the industry’s lowest power interconnect solutions. In addition, Sonics solutions include power management services that enable SoCs to cleanly control power state transitions including stopping clocks and/or switching off local supply voltages without risk of losing transactions or corrupting system states.
“Low power IP is critical in enabling power-efficient electronics,” said Pankaj Mayor, group director of Business Enablement at Cadence Design Systems, Inc. “We welcome Sonics to the Power Forward Initiative and look forward to incorporating their architectural perspective into the group. Working collaboratively, Sonics and other industry leaders in the Power Forward Initiative will enable customers to achieve their low-power goals.”
Sonics Director of Software Development, Scott Evans and Cadence Architect for IC Verification, Neyaz Khan will co-present a paper titled “CPF Flow for Highly-Configurable Interconnect IP” at this year’s CDNLive on September 9. This informative talk is part of CDN Live Track Two, Functional Verification B, at 2:15-3pm at the San Jose Convention Center. For more information about this event, please go to www.cadence.com/cdnlive.
About Power Forward Initiative
The Power Forward Initiative, which has more than 30 member companies, is an industry initiative sponsored by Cadence Design Systems and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross-section of the design chain, including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low Power Coalition in December 2006; CPF is now the most widely-deployed low-power intent standard in the industry and available from Si2. The Initiative has also published A Practical Guide to Low-Power Design – User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at www.powerforward.org.
About Sonics
Sonics Inc. is a premier supplier of SMART Interconnect solutions, delivering high SoC design predictability and increased design efficiency. Its solutions address the growing complexity found in consumer products with voice, data and video features. Major semiconductor and systems companies including Broadcom, Samsung, Texas Instruments and Toshiba leverage Sonics’ technology in leading products in the wireless, digital multimedia and communications markets. For more information, see www.sonicsinc.com.
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