English
Transceiver IP core
 |
Transceiver IP core
By
January 6, 2002 (10:42 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011203S0011
LaSer is a is a 10/40-Gbps serial transceiver IP block designed specifically for InfiniBand, SONET, and 10 Gigabit Ethernet chip designs. The IP core is available in quad, octal, and 16-channel configurations. It is currently being implemented in 0.18-ìm, 0.15-μm, and 0.13-μm processes from UMC and other foundries. Leda Systems, www.ledasystems.com
Related News
- Alphacore's Digital CMOS Impulse Ground-Penetrating Radar (GPR) Transceiver ASIC
- Bluetooth® V6.0 Channel Sounding RF Transceiver IP Core in 22nm & 40nm for ultra-low power distance aware Bluetooth connected devices
- Source Photonics Licenses 800G Transceiver Module Designs from Intel
- Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
- LeWiz Open Source LVDS Transceiver Design
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
|
E-mail This Article | 
|
|
Printer-Friendly Page |