Aldec offers Tcl/Tk integration tool
![]() |
Aldec offers Tcl/Tk integration tool
By Richard Goering, EE Times
December 28, 1999 (12:01 p.m. EST)
URL: http://www.eetimes.com/story/OEG19991228S0011
HENDERSON, Nev. Aldec Inc. has rolled out Tool Integrator, a product based on the Tcl/Tk scripting environment that gives users a way to integrate third-party synthesis and implementation tools into its Active-HDL environment. The offering makes it easier for Aldec, which does not offer synthesis, to provide a more complete design environment for programmable logic. Tool Integrator consists of some prewritten Tcl scripts that allow users to invoke third-party tools from within Active-HDL. "You can control your whole design from the Active-HDL environment," said Michael O'Brien, product marketing manager at Aldec. "It's a simplified way to have a GUI call your other tools."

Tcl is a scripting language for launching and controlling external applications. Tk is a graphical user interface tool kit. Tcl/Tk lets users customize design environments with out having to learn proprietary foreign language interfaces. O'Brien said users can download prepared scripts from Aldec's Web site, which support most major FPGA synthesis and layout tools. Users can create their own Tcl/Tk scripts to develop interfaces to other tools.
Once the scripts are installed, the third-party tools can be invoked from the Active-HDL tools menu. When launched, the third-party tools will have their own user interfaces.
Tool Integrator is built into Active-HDL PE (Plus Edition) 3.6, and it supports Tcl/Tk version 8.0. Active-HDL is currently based around VHDL simulation, with Verilog simulation promised for early 2000. There is no additional charge for Tool Integrator. Active-HDL PE prices start at $5,200.
Aldec is also announcing an expansion of its training program for VHDL and Verilog design. The company offers Web-based training, regional language training and on-site training. Aldec also provides free HDL training materials from its We b site.
Related News
- Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO for DO-254 Projects
- Dolphin Integration offers a live webinar on how to get an SoC power consumption under 0.5 uA in sleep mode
- Dolphin Integration offers a live webinar on the proven recipe for uLP SoC
- Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC Designs
- Dolphin Integration offers a webinar on "optimization of Power-Performance-Area from RTL-to-GDSII/Fab"
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |