Cadence Delivers Robust Portfolio of System-on-a-Chip Methodologies

IP News

Cadence Delivers Robust Portfolio of System-on-a-Chip Methodologies

SAN JOSE, Calif.----Dec. 15, 1999--Cadence Design Systems , the world's leading supplier of electronic design products and services, today announced the successful delivery of block-based design (BBD) and platform-based design (PBD) methodologies and tool flows to the Alba Centre in Scotland. BBD and PBD are the industry's first comprehensive set of fully codified, verified design methodologies that rapidly transition electronic product development into the emerging system-on-a-chip (SOC) realm.

``The BBD and PBD design methodologies, as well as the timing-driven design (TDD) methodology previously delivered by Cadence, represent important components of a complete SOC design environment,'' said Adriaan Ligtenberg, senior vice president of methodology services at Cadence.

The three SOC design methodologies delivered by Cadence are part of the curriculum taught today to engineering students in the Alba Centre's Institute for System Level Integration (ISLI). ``We appreciate the help that Cadence has given the Institute and its member universities to develop state-of-the-art design courses and projects in SOC technology for our curriculum,'' said Professor Steve Beaumont, ISLI director.

The SOC Leader

The BBD and PBD methodologies build on the successful introduction last year by Cadence of a fully integrated, timing-driven design methodology for the rapid creation of IP cores. All are part of the industry-wide evolution toward a fast, efficient approach to SOC design that can meet the accelerated time-to-market demands of today's consumer-driven electronics market.

To this end, Cadence has a skilled technical staff of more than 100 experts dedicated full-time to the development, verification and documentation of SOC methodologies. The team includes senior chip designers, software tool developers, and design methodology engineers with expertise in EDA tools, product design, and workflow management. Cadence has also leveraged the methodology expertise of this team, which successfully completed the BBD and PBD development programs and delivered them to the Alba Centre on schedule, in other groundbreaking customer engagements. One recently announced example is a project with Oki Semiconductor for implementing a custom IP reuse infrastructure. (See November 15, 1999, announcement: ``Cadence Builds IP Reuse Infrastructure for Oki Electric.'')

Advanced SOC Methodologies from Cadence

BBD is a hierarchical methodology for register-transfer level (RTL) design through tape-out. It covers project management, timing driven block authoring, hierarchical chip planning, top-level chip assembly, and hierarchical verification. It also includes methods for test, block-level validation, bus-based design, and design reuse. It is a fundamental building block for the Cadence PBD methodology.

PBD is a platform-based approach to SOC design. It builds upon the foundation of BBD to provide additional capability for embedded software design, analog block design, high level system design, rapid prototyping, and IP management. It also includes a reference multimedia design platform.

Alberto Sangiovanni-Vincentelli, chief technology adviser for Cadence and preface author of the book Surviving the SOC Revolution: A Guide to Platform-Based Design, stresses the importance of adopting a new approach to SOC design. ``As the complexity of the products under design increases, the development efforts increase exponentially,'' he said. ``To keep these efforts in check, a design methodology that favors reuse and early error detection is essential. Platform-based design, which is highly programmable and encompasses system and software reuse, leverages existing implementations available at all levels of abstraction. With this methodology, pre-existing components can be assembled with little or no effort.''

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are property of their holders.

Contact:
     Cadence Design Systems, Inc.
     In the U.S.:
     Lisa Gillette-Martin, 408/894-2512
     lgmartin@cadence.com
     In Europe:
     Andrew Thomas, +44 1344 865317
     athomas@cadence.com