MAPPER and TSMC Take Next Step in Exploring Multiple E-beam Lithography for IC Manufacturing at 22 nanometer node and Beyond
Delft, The Netherlands / Hsinchu, Taiwan -- Ocotober 13, 2008 -- MAPPER Lithography and Taiwan Semiconductor Manufacturing Company (TSMC) signed an agreement, according to which MAPPER will ship its first 300 mm multiple-electron-beam maskless lithography platform for process development and device prototyping to TSMC. This platform gives TSMC the opportunity to take the next step forward in exploring multiple e-beam technology as a lithography option at 22 nanometer and more advanced process nodes.
Multiple e-beam maskless lithography uses over 10,000 electron beams working in parallel to directly write circuit patterns on a wafer, eliminating the need for the costly photomasks used in current lithography machines.
“This is another huge step forward for MAPPER”, said MAPPER’s CEO, Dr. Christopher Hegarty. “We first demonstrated proof of principle of our massively parallel electron-beam maskless lithography technology concept in September 2007. In the near future we will be shipping our first 300 millimeter platform. We are very proud of this achievement. Having TSMC, the leading semiconductor foundry, as our launching customer for this project is a great honour for us. Their order also is a clear demonstration of TSMC’s expectation of our solution. Our whole team is fully committed to turning this opportunity for 22 nm manufacturing into a mature technology.”
Dr. Jack Sun, Vice President of Research and Development of TSMC said: “MAPPER’s technology holds great promise for cost-effective manufacturing at 22nm and beyond. We are therefore going to test MAPPER’s solution to see whether it will live up to its promise. Using this first tool we will be able to explore its viability for manufacturing. MAPPER’s solution is a serious candidate to become the future lithography standard.”
MAPPER’s technology
MAPPER develops lithography machines for the chip industry. These machines utilize a new and innovative technology with which the chips of the future can be made cost effectively. MAPPER´s machine provides a highly cost-effective way of making the next generation of chips because it significantly reduces costs by eliminating the photomask while simultaneously providing the ultimate in resolution and high productivity. MAPPER’s technology makes use of massively parallel electron beams (up to 13,000 beams in a full production system), thereby coupling the very high resolution and depth of field of electron beam with the promise of high throughput. Current lithography machines use photographic techniques to create minute electrical circuits smaller than 1/100th of a human hair on a silicon wafer. They use a mask which contains the blueprint of the chip and transfer this pattern on to a photosensitive layer (comparable to a photograph being exposed on film), however the photographic techniques have cost and resolution limitations for future generations of semiconductors.
About MAPPER Lithography
MAPPER’s offices are located in Delft, The Netherlands, near Delft University of Technology, one of the shareholders. MAPPER has a headcount of 160 people. Shareholders of MAPPER are besides Delft University of Technology professional investors – Capital-C Ventures, KT Venture Group, Quest for Growth and KBC Private Equity - and private investors.
About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of processproven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2008 is to exceed nine million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com
|
Related News
- TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
- Siemens extends support of multiple IC design solutions for TSMC's latest processes
- Synopsys IC Compiler II Certified for TSMC's Advanced 7-nm FinFET Plus Node
- ARM Offers Support For TSMC 7nm Manufacturing
- TSMC Certifies Synopsys IC Compiler II for the Most Advanced 7-nm Process Node Enabling Early Tapeouts
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |