Open-Silicon Introduces MAX Technologies
MILPITAS, CA-- November 12, 2008 -- Open-Silicon, Inc., the leading open market semiconductor manufacturer and provider of spec-to-silicon ASIC design services, today announced the introduction of three new MAX technologies to address design issues common to the 65nm and 40nm process nodes. Depending on each customer's needs Open-Silicon will use the PowerMAX™, CoreMAX™, and VariMAX™ technologies to build better custom silicon by designing in lower power, increased performance and managed process variability.
"The new MAX technology provides tremendous power and performance optimization advantages to our customers' products, regardless of the complexity of their designs," said Dr. Satya Gupta, VP engineering and co-founder, Open-Silicon. "By combining the ASIC industry's only transistor-level optimization flow with techniques like back biasing, which are new to the ASIC space, Open-Silicon can build the best possible fully custom silicon in smaller process geometries."
About MAX Technology
CoreMAX was created to build the fastest processor cores in the ASIC world. The CoreMAX technology comes out of the Open-Silicon acquisition of Zenasis Technologies in 2007 and uses over two million lines of C++ software and several patented techniques to move beyond the limitations of traditional library-based ASIC design. Built-in CoreMAX functions include design Boolean analysis and optimization, static timing, cell placement, route estimation, and simultaneous optimization at the logical, physical, and transistor levels. Based on the needs of each critical path in the design, CoreMAX may change cells, move cells, or even create new cells on-the-fly, performing a library-compatible layout for each new cell and characterizing these cells for use throughout the EDA environment. The new cells offer unique drive strengths and functionality that enable maximum device performance.
VariMAX addresses increasing process variability. Traditional approaches to variation management involve increased design margins and a large number of extraction and analysis corners. These approaches struggle in technologies like 65nm and 40nm where performance and leakage vary widely across a population of otherwise good devices. In order to manage this, Open-Silicon has implemented a back biasing design approach where the bulk transistor node voltage is controlled so that fast, leaky parts are reined in by adaptive calibration of the silicon.
PowerMAX enables design for the lowest possible power. Open-Silicon has already completed state-of-the-art 65nm designs using power savings methods like low-power place-and-route, voltage islands, power gating, clock gating, and multi-Vt. PowerMAX adds to this foundation with four new technologies: transistor level transformations, back biasing, power recovery, and custom leakage signoff. PowerMAX's transistor level optimization creates new standard cells on-the-fly to drive down both dynamic and leakage power. In addition to its variability control value, back biasing can also be employed whenever devices enter standby mode to further throttle back leakage power and prolong battery life. Power recovery operates late in the design phase to find timing paths with extra timing margin and replace cells with either higher Vt or lower drive strength equivalents. Finally, with custom leakage signoff Open-Silicon characterizes cell library leakage throughout the temperature range and then uses the actual design junction temperature for the leakage power calculation. Since the leakage power doubles every 15°C, this is required for accurate power estimation.
All three products are already silicon proven, or, as is the case with back biasing, currently in fab. All products are available for design use today.
About Open-Silicon
Open-Silicon, Inc. is a fabless ASIC company that was founded to set new standards for the predictability and reliability of ASICs and enable customers to differentiate their products through affordable custom silicon. Open-Silicon provides leading edge ASIC design, open market IP integration, and high quality silicon manufacturing services to customers worldwide. Through the "Science of ASICs" initiative Open-Silicon continues to introduce technology advantages that help customers increase their market success. For more information, visit Open-Silicon's website at www.open-silicon.com or call 408-240-5700.
|
Related News
- Open-Silicon Introduces "On Time, or On Us" Program
- Open-Silicon Releases Max Technology 2.0
- Open-Silicon Introduces Multi-Layer Mask Program: Reduces Mask Costs by up to 50% for 90nm and Smaller Lithographies
- Open-Silicon Introduces IC-Catalyst - an Integrated Platform for Chip Design and Manufacturing
- SiPearl and Open-Silicon Research Collaborate to Accelerate Custom Silicon for High Performance Computing (HPC) Applications
Breaking News
- Siemens delivers certified and automated design flows for TSMC 3DFabric technologies
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |