SIA road map defines performance-SoC challenges

SIA road map defines performance-SoC challenges
By J. Robert Lineback, Semiconductor Business News
November 23, 1999 (5:22 p.m. EST)
URL: http://www.eetimes.com/story/OEG19991123S0046

SAN JOSE, Calif. — Semiconductor technologist are becoming concerned about the industry's ability to deliver a new class of powerful system-on-chip products, identified as "performance SoC" in the 1999 International Technology Roadmap for Semiconductors, released Monday (Nov. 22) by the Semiconductor Industry Association (SIA).

In previewing the new international road map, representatives with the SIA suggested that a whole new category of "P-SoC" products was emerging and required the development of different technologies and architectures than today's "cost-effective SoC" designs.

Growing concerns revolve around challenges in "maintaining a rate of improvement in electrical performance of about two-times every two years in high-performance components," said the 1999 International Technology Roadmap for Semiconductors, which charts requirements and possible solutions for chip making over the next 15 years.

Despite development of new solid-state materials for transistors and interconnects, SoC designs are not now keeping pace with the high-performance requirements of next-generation systems, said Robert R. Doering, senior fellow in the Silicon Technology Development department of Texas Instruments Inc., who participated in the road map press briefing on Monday. In an interview after the SIA's briefing, Doering said the 1999 edition of the chip road map has added a new section that calls for new design approaches and SoC architectures to help "hedge the bet" in delivering higher performance system-level integration.

"It's becoming increasingly difficult to make transistors faster and the wiring that connects them lower in capacitance. To increase the overall speed of chips, we are going to need different approaches than just raw [improvements] to wiring and transistor technologies," Doering said. "We need to start looking at designs and architectures that buy sheer performa nce when integrating more functions on a chip."

The 1999 semiconductor road map suggests that "innovations in the techniques used in circuit and system design will be essential to maintain the historical trends in performance improvement. It is expected that integration of multiple silicon technologies on the same chip and a closer integration of package and silicon technology will be necessary" for the emerging P-SoC category, according to the new SIA document.

Doering said the road map committees defined two different classes of SoC products in the coming decade: cost-effective and performance designs. The cost-effective designs have been dubbed "C-SoC."

The C-SoC and P-SoC designs are similar in that they combine historically separate component functions on a single silicon die — such as digital, analog, mixed-signal, and DRAM — but "fundamentally, the drivers are different in these two cases," Doering said. "The cost effective [C-SoC] is more in the neighborhood of what you are seei ng in today's system-on-chip designs, which is really going into things like cellular phones and other digital wireless products, like pagers, PDAs," he said. "The main emphasis is on low power and functionality, compactness and low cost. The other [P-Soc] is a regime that is just now emerging."

Some of the solutions for higher performance SoC designs could track developments in fast microprocessors, which have greater levels of parallelism in the chip architecture. "It is analogous to what's happening in microprocessor designs as they get effectively more powerful for a given megahertz [of speed] just by doing more pipelining," Doering said. "As the architectures get more sophisticated, the processors take on more parallelism. That's another way to get more performance with everything else being equal."