English
Verayo Secures FPGAs with Silicon Signatures
PALO ALTO, Calif.-- December 10, 2008 -- Verayo, a security and authentication solutions provider, today announced the availability of its new Soft PUF technology for FPGAs and FPGA-based systems. Soft PUF extracts chip-unique signatures to authenticate the FPGA silicon, the underlying board or system. These chip-unique signatures are also used as dynamic, unique and volatile secret keys to enable new security applications not previously possible on the FPGA platform.
PUF, a kind of “silicon biometrics” technology, extracts unique signatures of a silicon chip for authentication and security applications. The Soft PUFs are PUFs implemented in existing off-the-shelf FPGA devices to extract the unique signatures of the FPGA silicon. Soft PUFs do not require any modifications to the FPGA silicon or design tools.
The chip-unique signatures extracted by Soft PUFs enable a strong protection against counterfeiting and over-building of FPGAs and/or FPGA-based systems. The same chip-unique signatures are also used as dynamically-generated, unique and volatile cryptographic keys to provision secure applications, or to control access to features and functions tied to the individual FPGA silicon. This enables Soft PUFs to elevate security, flexibility and reduce the cost of product development, which are particularly useful where market pressures or production volumes do not justify spinning an ASIC.
“Verayo is taking the trust and security of the FPGA platform to a new high,” said Anant Agrawal, CEO of Verayo. “With the release of our RFID product last September, we have already demonstrated how PUFs provide a cost-effective way to elevate the security and trust in SOCs. Now, for the first time, PUFs have been programmed into existing FPGA devices to make the FPGAs a more secure, flexible and cost-effective platform for product development.”
Verayo is introducing the application of its PUF technology for FPGAs at the FPGA Summit in San Jose this week. Verayo’s Senior Design Engineer, Mandel Yu, will deliver his presentation “Exploiting Uniqueness of FPGA Silicon for Security Applications” on December 11.
About Verayo
Verayo was founded in Silicon Valley in 2005. The company is focused on building security and authentication solutions based on Silicon Physical Unclonable Functions (PUF) technology, which was invented and first implemented at MIT by Prof. Srini Devadas and his team. Since its founding, the Verayo team has designed, built, and tested ICs using PUFs and built-up a growing body of additional IP and substantive know-how beyond the initial IP that Verayo licensed exclusively from MIT. Verayo is funded by Khosla Ventures and has assembled an experienced Advisory Board drawn from the semiconductor and security industries. In addition to developing commercial products, the company is working on projects for various U.S. Defense Agencies.
PUF, a kind of “silicon biometrics” technology, extracts unique signatures of a silicon chip for authentication and security applications. The Soft PUFs are PUFs implemented in existing off-the-shelf FPGA devices to extract the unique signatures of the FPGA silicon. Soft PUFs do not require any modifications to the FPGA silicon or design tools.
The chip-unique signatures extracted by Soft PUFs enable a strong protection against counterfeiting and over-building of FPGAs and/or FPGA-based systems. The same chip-unique signatures are also used as dynamically-generated, unique and volatile cryptographic keys to provision secure applications, or to control access to features and functions tied to the individual FPGA silicon. This enables Soft PUFs to elevate security, flexibility and reduce the cost of product development, which are particularly useful where market pressures or production volumes do not justify spinning an ASIC.
“Verayo is taking the trust and security of the FPGA platform to a new high,” said Anant Agrawal, CEO of Verayo. “With the release of our RFID product last September, we have already demonstrated how PUFs provide a cost-effective way to elevate the security and trust in SOCs. Now, for the first time, PUFs have been programmed into existing FPGA devices to make the FPGAs a more secure, flexible and cost-effective platform for product development.”
Verayo is introducing the application of its PUF technology for FPGAs at the FPGA Summit in San Jose this week. Verayo’s Senior Design Engineer, Mandel Yu, will deliver his presentation “Exploiting Uniqueness of FPGA Silicon for Security Applications” on December 11.
About Verayo
Verayo was founded in Silicon Valley in 2005. The company is focused on building security and authentication solutions based on Silicon Physical Unclonable Functions (PUF) technology, which was invented and first implemented at MIT by Prof. Srini Devadas and his team. Since its founding, the Verayo team has designed, built, and tested ICs using PUFs and built-up a growing body of additional IP and substantive know-how beyond the initial IP that Verayo licensed exclusively from MIT. Verayo is funded by Khosla Ventures and has assembled an experienced Advisory Board drawn from the semiconductor and security industries. In addition to developing commercial products, the company is working on projects for various U.S. Defense Agencies.
|
||||||
Related News
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- IP block secures FPGAs with one external IC
- Think Silicon secures Seed investment round led by Metavallon VC
- Microsemi Collaborates with Silicon Creations to Enable Industry's Lowest Power FPGA 12.7G Transceivers With PHYs for Microsemi's PolarFire FPGAs
- 3-D FPGAs enable silicon convergence
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- YorChip announces patent-pending Universal PHY for Open Chiplets
|
E-mail This Article | 
|
|
Printer-Friendly Page |