Faraday Offers the Miniaturized Cell Library miniLib in both 90nm and 65nm

Approximately 15% area- and power-saving without sacrificing performance leads the new cell libraries into market penetration of traditional generic ones

Hsinchu, Taiwan - Decomber 18, 2008 -- Faraday Technology Corporation (TAIEX: 3035) today announced the availability of the commercial 90nm and 65nm miniaturized cell libraries, miniLib™, in both standard process (SP) and low leakage (LL). The advantage of miniLib™ is its core area reduction, up to 15% in various cases, and still keeping all the merits of their corresponding generic cell libraries. These two miniLib™ has been silicon proven via many function verification through real chips.

From the statistic data derived through real case implementation, these miniLib™ can achieve 15% area saving in general applications. They are good to the size-sensitive designs for further area improvement, such as networking platform, wireless baseband and multimedia processors, etc. Furthermore, the size reduction will not sacrifice the performance, and simultaneously, the dynamic power and static power can be reduced to 15% and 20% respectively (in 90nm SP as example). Both area and power benefits are shown in implementing with miniLib™.

"As a leading silicon IP provider, Faraday have been devoted to miniaturized library development since 0.18um," said Eliot Chen, Associate Vice President of RD at Faraday. "The launch of 90nm and 65nm miniLib™ indicates Faraday's another great milestone in our technology advancement in deep sub-micron area. This is achieved through our accumulated experience for years in cell design and layout, especially for flip flop miniaturization, and these effective solutions are expected to assist our customers to design their competitive and differentiated products," he added.

These miniLib™ are equipped with two different transistor–voltage-thresholds, regular-voltage -threshold (RVT) and high-voltage-threshold (HVT), in both SP and LL processes for customers' choice, depending on their performance and power requirements. Also, the fusion of SP and LL can be done in 90nm. Furthermore, in order for easy routing, the pin accessibility to each cell is well arranged; the routing efficiency will not be sacrificed at all due to the size reduction.

"We are very glad to offer such ideal and competitive cell libraries in the deep sub-micron market," said Steve Wang, Chief Strategy Officer at Faraday. "The market trend and customer demand for low power and die size are key drivers to Faraday's 90nm and 65nm miniLib™ development. We have got several design-win cases now, covering various applications, and have high confidence that these new cell libraries will bring more market successes soon to us and our customers."

Availability

Faraday's miniLib™ for 90nm and 65nm in both SP and LL are now available.

About Faraday Technology Corporation

Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2007 revenue of US$ 156 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: www.faraday-tech.com.