Aldec forms Partnership with Alatek IP Design House

IP News

Aldec forms Partnership with Alatek IP Design House

Henderson, Nevada, November 11, 1999 -- Aldec, Inc., a leading supplier of HDL design entry and verification software for programmable logic designs, announced today the addition of Alatek Inc. to the Aldec IP Partner (AIPP) Program. The partnership will bring streamlined implementation of Alatek IP Cores into the Active-HDL environment. Future partnership features will provide documentation and application notes for Aldecís Active-HDL users, working with Alatek IP.

"Partnerships between IP providers and design and verification software companies are very important to the entire PLD market. Besides speeding up time-to-market, it will ease the transition of IP Core usage in everyday design". Quoted Witold Fendrych, Alatek IP Marketing Manager.

Impact on the Industry

As more IP development companies become involved with EDA vendors, more complicated and sophisticated systems can be developed based on FPGA structures. This fact can force FPGA vendors to create more complex and higher density hardware devices.

The integration between ALATEK cores and Aldecís Active-HDL simulator will be highly efficient. ALATEK will provide pre-compiled ready-to-use libraries for its Cores to be used in the environment. The Active-HDL Block Diagram Editor allows the user to create complex designs based on IP cores in only seconds. Simulation of designs with ALATEK Cores will become much easier with the usage of prepared, technology-dependent EDIF netlists. In addition, ALATEK will deliver appropriate application notes and technical tips on core implementation and the usage with Aldec simulation tools.

ABOUT ALATEK

Alatek is an engineering company specialized in programmable logic-based electronic systems. The company provides VHDL synthesizable industry-standard Intellectual Property (IP) cores for popular FPGA devices. Alatek offers high quality, low cost synthesizable cores for devices such as microcontrollers, PC peripherals, bus interfaces, and their free simulation models. Because Alatek has excellent expertise in design simulation and verification, especially for Altera and Xilinx FPGA structures, Alatek engineers create a full-service design house. Although Alatek develops their own cores, cores are also developed for other companies designing in VHDL.

About Aldec

Aldec has offered PC-based design entry and simulation solutions to FPGA designers for more then 15 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY) Aldec, Inc., headquartered in Henderson, Nevada, produces a universal suite of Windows based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the Windows-based EDA market as the fastest growing privately held EDA supplier in the world. Additional information about Aldec is available at http://www.aldec.com.

Active-HDL and Active-CAD are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.