English
LatticeECP2M FPGA Enables Low Cost PCI Express Bridge for VOIP Platforms Based on Intel Architecture
HILLSBORO, OR - MARCH 2, 2009 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the availability of a low cost programmable PCI Express-to-High Speed Serial (HSS) bridge for the CAP12-120, a Small Office Home Office (SOHO) Voice Over IP (VOIP) platform running on Intel® architecture. This bridge design has been implemented in the award-winning LatticeECP2M™ FPGA. The solution utilizes the LatticeECP2M's low power, high-performance SERDES and a Lattice PCI Express Intellectual Property (IP) core.
"The LatticeECP2M PCI Express to HSS Bridge is a great example of how Lattice provides powerful yet economical bridge solutions for a variety of applications," said Sean Riley, Lattice Corporate Vice President of High Density Solutions. "We are focused on providing the tools and flexible platforms that enable our customers to build applications based on their requirements. The LatticeECP2M family provides a very cost-effective alternative to the high-end SERDES-based FPGAs and ASSPs that traditionally have been used for PCI Express applications. The economical yet powerful LatticeECP2M family allows designers to develop designs incorporating next generation interfaces like PCI Express quickly."
The Lattice FPGA solution is used in the Intel® CAP12-120 reference design, based on the Intel® Celeron® M 915GM processor and chipset. To address the voice, video and data communications needs of small and medium businesses and enterprises (SMB/SMEs), Intel has added two versatile yet affordable Multi System Business Gateway reference designs to its family of converged solutions platforms. Announced at VoiceCon 2008, the Intel CAP12-120 is a proof-of-concept design for software-based IP-PBX/MSBG solutions that enables developers to build a converged communications device for up to 120 seats quickly and cost effectively. These all-in-one-box solutions are capable of delivering a variety of services and can be scaled and modified easily in software to meet the requirements of different customer premises. The fully integrated platforms include all the necessary hardware and software components for building cost effective IP-PBX/MSG solutions, reducing the time, effort and development cost of these platforms.
The LatticeECP2M family provides an ideal FPGA platform for implementation of high performance serial protocols such as PCI Express and Gigabit Ethernet. The Lattice PCI Express IP, combined with Lattice's own high-speed SERDES and the economical, low power, high-performance LatticeECP2M fabric, provides designers a powerful platform for satisfying their high-performance bridging and co-processing needs. The flexibility of the LatticeECP2M fabric provides designers with a platform to develop a variety of applications while still meeting very aggressive cost targets.
About the LatticeECP2M FPGA Family
The low power LatticeECP2M FPGA family has redefined the mid-range FPGA product category by providing performance-enhancing features that are typically available only on more expensive competitive high-end FPGAs. The LatticeECP2M family supports logic densities from 20K LUTs up to 100K LUTs, has high performance DSP blocks, supports DDR2 memory interfaces at 533Mbps and up to 840Mbps generic LVDS performance. Some of the high-end features incorporated into the LatticeECP2M family include embedded SERDES I/O and the most on-chip memory in its class. The LatticeECP2M family supports up to 16 channels of embedded SERDES, operating up to 3.125Gbps. The SERDES supports protocols such as PCI Express, Ethernet (1GbE and SGMII), CPRI/OBSAI, SMPTE and JESD204. In addition to embedded SERDES channels, the LatticeECP2M FPGA family offers Embedded Block RAM capacity ranging from 1.2 Mbits to 5.3 Mbits, representing up to a 400% increase over competitive low-cost architectures.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD and Mixed Signal programmable logic solutions. For more information, visit www.latticesemi.com
"The LatticeECP2M PCI Express to HSS Bridge is a great example of how Lattice provides powerful yet economical bridge solutions for a variety of applications," said Sean Riley, Lattice Corporate Vice President of High Density Solutions. "We are focused on providing the tools and flexible platforms that enable our customers to build applications based on their requirements. The LatticeECP2M family provides a very cost-effective alternative to the high-end SERDES-based FPGAs and ASSPs that traditionally have been used for PCI Express applications. The economical yet powerful LatticeECP2M family allows designers to develop designs incorporating next generation interfaces like PCI Express quickly."
The Lattice FPGA solution is used in the Intel® CAP12-120 reference design, based on the Intel® Celeron® M 915GM processor and chipset. To address the voice, video and data communications needs of small and medium businesses and enterprises (SMB/SMEs), Intel has added two versatile yet affordable Multi System Business Gateway reference designs to its family of converged solutions platforms. Announced at VoiceCon 2008, the Intel CAP12-120 is a proof-of-concept design for software-based IP-PBX/MSBG solutions that enables developers to build a converged communications device for up to 120 seats quickly and cost effectively. These all-in-one-box solutions are capable of delivering a variety of services and can be scaled and modified easily in software to meet the requirements of different customer premises. The fully integrated platforms include all the necessary hardware and software components for building cost effective IP-PBX/MSG solutions, reducing the time, effort and development cost of these platforms.
The LatticeECP2M family provides an ideal FPGA platform for implementation of high performance serial protocols such as PCI Express and Gigabit Ethernet. The Lattice PCI Express IP, combined with Lattice's own high-speed SERDES and the economical, low power, high-performance LatticeECP2M fabric, provides designers a powerful platform for satisfying their high-performance bridging and co-processing needs. The flexibility of the LatticeECP2M fabric provides designers with a platform to develop a variety of applications while still meeting very aggressive cost targets.
About the LatticeECP2M FPGA Family
The low power LatticeECP2M FPGA family has redefined the mid-range FPGA product category by providing performance-enhancing features that are typically available only on more expensive competitive high-end FPGAs. The LatticeECP2M family supports logic densities from 20K LUTs up to 100K LUTs, has high performance DSP blocks, supports DDR2 memory interfaces at 533Mbps and up to 840Mbps generic LVDS performance. Some of the high-end features incorporated into the LatticeECP2M family include embedded SERDES I/O and the most on-chip memory in its class. The LatticeECP2M family supports up to 16 channels of embedded SERDES, operating up to 3.125Gbps. The SERDES supports protocols such as PCI Express, Ethernet (1GbE and SGMII), CPRI/OBSAI, SMPTE and JESD204. In addition to embedded SERDES channels, the LatticeECP2M FPGA family offers Embedded Block RAM capacity ranging from 1.2 Mbits to 5.3 Mbits, representing up to a 400% increase over competitive low-cost architectures.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD and Mixed Signal programmable logic solutions. For more information, visit www.latticesemi.com
|
||||||
Related News
- Lattice Announces First PCI Express 2.0 Compliant Low Cost FPGA
- Tokyo Electron Device Announces simultaneous release of three high-density FPGA PCI express platforms
- Lattice Accelerates PCI Express System Design With New Low Cost LatticeECP2M Development Kit
- Smartlogic PCI Express DMA IP Cores now available for Intel FPGAs
- Toshiba Announces Immediate IP Subsystem Availability of PCI Express and DDR3 for Custom LSI Platforms
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |