English
Altera and Tensilica Announce the Xtensa(tm) Microprocessor Core Now Available for APEX(tm) Devices
IP News
Editor Contacts:
"This new development represents a major breakthrough in System-on-a-Programmable- Chip(tm) design," said Craig Lytle, senior director of Altera's intellectual property business unit. "Utilizing the Xtensa processor on high-density APEX devices will give designers the ability to perfect the processor to meet the individual performance and feature requirements of their particular applications."
"We are very excited about being able to support the microprocessor needs of the programmable logic design community by providing an automated path for an optimized APEX netlist," said Bernie Rosenthal, vice president of Tensilica marketing and business development. "This new development will provide Altera customers with access to our Xtensa technology, and enable them to realize systems on a programmable chip, utilizing the extraordinary configurability and flexibility inherent in our processor core and its robust instruction set architecture."
Xtensa Processor Core
The Xtensa configurable processor is a 32-bit synthesizable CPU core based upon a rich instruction set architecture. Using Tensilica Instruction Extension ("TIE") language, designers can incorporate their own system-specific instructions to further customize their design. Designers can modify the feature set of the processor, including cache sizes, write buffer sizes, address and data bus widths, and other core parameters. One of the most important features of Xtensa is the automated creation of a complete software development tool environment individually tailored to each processor configuration. Tensilica's software development suite features a C/C++ compiler, an assembler, a linker, a debugger, a cycle-accurate instruction-set simulator, and a code profiler.
About the APEX PLD Family
The Xtensa microprocessor core has been optimized for the APEX 20K400 device and higher-density devices. The EP20K400 device is fabricated on a 0.25-micron (drawn), six-layer metal SRAM process and features 16,640 logic elements, 104 embedded system blocks, and up to 1664 macrocells and 212,992 bits of on-chip RAM for a combined total of approximately 400,000 gates, or a maximum of 1,052,000 system gates.
All devices in the APEX family feature Altera's unique MultiCore(tm) architecture, which combines look-up table logic, product-term logic and embedded memory into MegaLAB(tm) blocks. Each MegaLAB block is connected to all other MegaLAB blocks in the device via Altera's continuous FastTrack(r) Interconnect routing structure. Each embedded system block (ESB) within a MegaLAB block contains 2,048 programmable bits; these bits can be configured to support product-terms, dual-port RAM or ROM.
Availability and Pricing
Tensilica's Xtensa AMPP microprocessor core is available directly through Tensilica. The Xtensa will be available with the features selection and test-drive options through Tensilica's web site in Q4 1999. The license fee for the use of the Xtensa IP under the Altera AMPP program is $74,000 for a single-node one-year royalty free license.
About Tensilica
Tensilica was founded in July 1997 to address the fast growing market for application-specific microprocessor cores and software development tools in high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-a-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company has over 50 engineers engaged in research, development, and customer support from its offices in Santa Clara, California, Waltham, Massachusetts, and Yokohama, Japan. For more information about Tensilica visit the World Wide Web at http://www.tensilica.com
About AMPP The Altera Megafunction Partners Program, established in August 1995, was created to bring the advantages of design reuse to users of Altera PLDs. AMPPSM is an alliance between Altera and developers of intellectual property (IP) cores that encourages megafunction development. Altera provides technical information and training to AMPP partners, who create and support IP cores targeted for Altera programmable logic devices. There are 27 partners who offer 91 megafunctions; customers may automatically request a free evaluation of any of these IP cores by selecting the Altera Alliances link at the Altera web site: http://www.altera.com.
About Altera
Altera Corporation, The Programmable Solutions Company(tm), was founded in 1983 and is a leading supplier of programmable logic devices and associated logic development software tools. Programmable logic devices are semiconductor chips that can be programmed on-site, using software tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. Altera's CMOS-based programmable logic devices address high-speed, high-density and low-power applications in the telecommunications, data communications, computer peripheral, and industrial markets. Altera common stock is traded on the Nasdaq Stock Market under the symbol ALTR. More information on Altera can be obtained on the Internet at http://www.altera.com.
###
Altera, The Programmable Solutions Company, AMPP, APEX, System-on-a-Programmable-Chip, MultiCore, MegaLab, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. Tensilica and Xtensa are trademarks belonging to Tensilica Inc. All other trademarks are the property of their respective holders.
Editor Contacts:
| Rhondalee Rohleder Altera Corporation (408) 544-8296 rrohlede@altera.com | Kristin Hehir Tsantes & Associates (408) 369-1500 kristin@tsantes.com | Kim Alfaro The Leapfrog Group (415) 563-4769 kimpr@holonet.net |
Altera and Tensilica Announce the Xtensa(tm) Microprocessor Core Now Available for APEX(tm) Devices
- APEX-Optimized 32-bit Configurable Processor for Altera's Megafunction Partner Program (AMPP SM)
- High Performance MPU for Embedded Systems
- Web-based Xtensa Generator will Provide MPU Features Selection and Test-Drive
"This new development represents a major breakthrough in System-on-a-Programmable- Chip(tm) design," said Craig Lytle, senior director of Altera's intellectual property business unit. "Utilizing the Xtensa processor on high-density APEX devices will give designers the ability to perfect the processor to meet the individual performance and feature requirements of their particular applications."
"We are very excited about being able to support the microprocessor needs of the programmable logic design community by providing an automated path for an optimized APEX netlist," said Bernie Rosenthal, vice president of Tensilica marketing and business development. "This new development will provide Altera customers with access to our Xtensa technology, and enable them to realize systems on a programmable chip, utilizing the extraordinary configurability and flexibility inherent in our processor core and its robust instruction set architecture."
Xtensa Processor Core
The Xtensa configurable processor is a 32-bit synthesizable CPU core based upon a rich instruction set architecture. Using Tensilica Instruction Extension ("TIE") language, designers can incorporate their own system-specific instructions to further customize their design. Designers can modify the feature set of the processor, including cache sizes, write buffer sizes, address and data bus widths, and other core parameters. One of the most important features of Xtensa is the automated creation of a complete software development tool environment individually tailored to each processor configuration. Tensilica's software development suite features a C/C++ compiler, an assembler, a linker, a debugger, a cycle-accurate instruction-set simulator, and a code profiler.
About the APEX PLD Family
The Xtensa microprocessor core has been optimized for the APEX 20K400 device and higher-density devices. The EP20K400 device is fabricated on a 0.25-micron (drawn), six-layer metal SRAM process and features 16,640 logic elements, 104 embedded system blocks, and up to 1664 macrocells and 212,992 bits of on-chip RAM for a combined total of approximately 400,000 gates, or a maximum of 1,052,000 system gates.
All devices in the APEX family feature Altera's unique MultiCore(tm) architecture, which combines look-up table logic, product-term logic and embedded memory into MegaLAB(tm) blocks. Each MegaLAB block is connected to all other MegaLAB blocks in the device via Altera's continuous FastTrack(r) Interconnect routing structure. Each embedded system block (ESB) within a MegaLAB block contains 2,048 programmable bits; these bits can be configured to support product-terms, dual-port RAM or ROM.
Availability and Pricing
Tensilica's Xtensa AMPP microprocessor core is available directly through Tensilica. The Xtensa will be available with the features selection and test-drive options through Tensilica's web site in Q4 1999. The license fee for the use of the Xtensa IP under the Altera AMPP program is $74,000 for a single-node one-year royalty free license.
About Tensilica
Tensilica was founded in July 1997 to address the fast growing market for application-specific microprocessor cores and software development tools in high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-a-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company has over 50 engineers engaged in research, development, and customer support from its offices in Santa Clara, California, Waltham, Massachusetts, and Yokohama, Japan. For more information about Tensilica visit the World Wide Web at http://www.tensilica.com
About AMPP The Altera Megafunction Partners Program, established in August 1995, was created to bring the advantages of design reuse to users of Altera PLDs. AMPPSM is an alliance between Altera and developers of intellectual property (IP) cores that encourages megafunction development. Altera provides technical information and training to AMPP partners, who create and support IP cores targeted for Altera programmable logic devices. There are 27 partners who offer 91 megafunctions; customers may automatically request a free evaluation of any of these IP cores by selecting the Altera Alliances link at the Altera web site: http://www.altera.com.
About Altera
Altera Corporation, The Programmable Solutions Company(tm), was founded in 1983 and is a leading supplier of programmable logic devices and associated logic development software tools. Programmable logic devices are semiconductor chips that can be programmed on-site, using software tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. Altera's CMOS-based programmable logic devices address high-speed, high-density and low-power applications in the telecommunications, data communications, computer peripheral, and industrial markets. Altera common stock is traded on the Nasdaq Stock Market under the symbol ALTR. More information on Altera can be obtained on the Internet at http://www.altera.com.
###
Altera, The Programmable Solutions Company, AMPP, APEX, System-on-a-Programmable-Chip, MultiCore, MegaLab, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. Tensilica and Xtensa are trademarks belonging to Tensilica Inc. All other trademarks are the property of their respective holders.
Related News
- Mentor Graphics Enhanced XRAY® Debugger Available Immediately For The Tensilica® Xtensa® Microprocessor
- Altera and New AMPPSM Partner ARC Cores Announce Configurable RISC Processor For APEX(tm) 20K Devices <!--<FONT SIZE=-1>(by Peter Clarke - EE-TIMES)</FONT>-->
- Eureka Technology IP Cores Now Available for Altera's ARM®-Based Excalibur[tm] Devices
- Micrium uC/OS-II RTOS Support Now Available for Tensilica’s Diamond Standard and Xtensa Configurable Processors
- SRS WOW XT and SRS XSPACE 3D Now Available on Tensilica's Xtensa HiFi 2 Audio Engine for Mobile Phones
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |