Motorola Unveils Plans for First Star*Core-Based Product

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Motorola Unveils Plans for First Star*Core-Based Product

MSC8101 is the industry's first DSP optimized for the "packetized" world, supporting ATM, Fast-Ethernet and fast TDM highways
 
AUSTIN, Texas -- September 13, 1999

A new digital signal processor (DSP) from Motorola, (NYSE: MOT) featuring an on-chip network interface, is the first to use Motorola's new Star*Core™ DSP core technology. This new product represents a dramatic leap in DSP technology, surpassing previously available devices in performance, networking capabilities, compiler efficiency, flexibility, and power efficiency. Developers of next-generation communication and networking infrastructure will soon be able to use this new Star*Core SC140-based DSP in all types of high-performance networking DSP applications.

The MSC8101, with a 300 MHz DSP core, offers four Arithmetic Logic Units (ALUs) providing 1200 DSP MIPS (3000 RISC MIPS), a high-performance 150 MHz Communications Processor Module (CPM) programmable network protocol engine, 512KB (256K 16-bit words) of on-chip Static RAM (SRAM), a 100 MHz 64- or 32-bit PowerPC™ bus interface, and a programmable memory controller. On-chip peripherals such as a 300 MHz Enhanced Filter Coprocessor (EFCOP) and a powerful centralized DMA engine push performance even higher.

The MSC8101 is the first DSP manufactured using Motorola's new 0.13 micron copper interconnect process technology. It operates with a 1.5 V core and an independent 3.3 V I/O power supply, dissipating about 500mW of power for the entire device, all in a space-saving 17mm x 17mm plastic package.

The definition of the MSC8101 was driven by the next revolution in the communication world. As the transition from analog to digital systems is well on the way, the next revolution will take us from the circuit switched networks to packet switched networks. In addition to today's packetized data, tomorrow's system must handle packetized real-time streams such as speech and video. DSPs, which have always been optimized for real-time applications, will be required to interface to packetized backbones such as 155 Mbps ATM backplanes. Motorola's MSC8101, equipped with its unique programmable 32-bit RISC CPM, runs the networking protocol layers, thereby enabling the MSC8101 to link directly to packetized backbones, such as ATM and Fast Ethernet, as well as PCM highways such as E1/T1 and E3/T3. This powerful CPM engine is based on the CPM from Motorola's popular PowerQUICC™ II (MPC8260) networking microcontrollers, used by all of the leading top-ten networking companies.

To minimize time-to-market, the MSC8101 utilizes the compiler-efficient SC140 core, the most compiler friendly DSP core in the industry, equipped with top-of-the-line software development tools. To minimize hardware development time, the MSC8101 is equipped with a well-proven, industry-standard, PowerPC (60x-compatible) bus. At 100 MHz bus operating speed and 64- or 32-bit width (programmable), the PowerPC bus enables the MSC8101 to easily hook to PowerPC bus devices and shared memory sub-systems. Additional system interface flexibility is provided through a separate enhanced 16-bit parallel Host Interface (HID16) that supports a variety of microcontroller, microprocessor, and DSP bus interfaces in conjunction with the PowerPC bus interface.

Infrastructure systems are driven by performance density. To minimize board space requirements, the MSC8101 integrates four megabits (512K bytes) of on-chip zero-wait-state memory, which holds the program and data required in many of the target applications. This on-chip memory may eliminate or reduce accesses to off-chip memory, increasing system performance and lowering system power consumption and cost.

To maximize the number of channels each MSC8101 can process, the device integrates the Enhanced Filter Coprocessor (EFCOP), which boosts performance in filtering operations vital to such DSP tasks as echo cancellation. A sophisticated 16-channel DMA engine offloads the core from all data shuttling in the system. To further reduce board space requirements, the MPC8101 comes in a 17mm x17mm plastic package.

The MSC8101 is the first product in the industry to offer this combination of DSP, PowerPC, and CPM technologies all in a single integrated device. It is Motorola's unique position in the industry to offer such capabilities for the communications and networking infrastructure market.

"The MSC8101 consists of an extremely powerful DSP engine that has been married with Motorola's market-leading communications processor architecture and its widely-supported PowerPC bus," said DSP market watcher Will Strauss, president of Forward Concepts (Tempe, AZ). He went on to say, "The MSC8101 opens the door for distributed systems where the DSP processes the data directly from the network stream."

"Our MSC8101 is the first chip to integrate the SC140 DSP core unveiled by the Star*Core alliance last April," said Daniel Artusi, vice president and general manager of Motorola's Networking and Computing Systems Group. "This is a genuine breakthrough for performance-intensive applications in wireless and wireline infrastructure equipment such as Internet telephony gateways, next-generation digital cellular infrastructure systems, xDSL telephone equipment, and multi-channel modem banks. It also demonstrates Motorola's System On a Chip (SOC) initiative to integrate our rich library of leadership intellectual property into single-chip solutions."

MSC8101 Key Features

SC140 Core

• Architecture optimized for efficient C/C++ code compilation
• Four 16-bit ALUs and two 32-bit AGUs
• 1200 DSP MIPS, 3000 RISC MIPS, running at 300 MHz
• Very low power dissipation - less than 0.25W for the core running full speed at 1.5 V
• Variable Length Execution Set (VLES) execution model
• JTAG/Enhanced OnCE debug port

150 MHz Communications Processor Module (CPM)

• Programmable protocol machine uses a 32-bit RISC engine
• 155 Mbps ATM interface (including AAL 0/1/2/5)
• 10/100 Mbit Ethernet interface
• Up to four E1/T1 interfaces or; one E3/T3 interface and one E1/T1 interface
• HDLC support up to T3 rates, or 256 channels

100MHz 64- or 32-bit wide PowerPC Bus interface

• Supports bursts for higher efficiency
• Glueless interface to PowerPC bus systems
• Multi-master support

Programmable Memory Controller

• Controls up to eight banks of external memory
• User programmable machines (UPM) allows glueless interface to various memory types -SRAM, DRAM, EPROM, FLASH, and other user-definable peripherals
• Dedicated pipelined SDRAM memory interface

Large On-chip SRAM

• 256K 16-bit words (512K Bytes)
• Unified program and data space configurable by the application
• Word and byte addressable

DMA controller

• 16 DMA channels, FIFO based, with burst capabilities
• Sophisticated addressing capabilities

Small foot print package

• 17mm x 17 mm plastic package

Very low power consumption

• Estimated power consumption for the entire device is 500mW
• Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)

Enhanced Filter Coprocessor

• Independently and concurrently executes long filters (such as echo cancellation)
• Runs at 300 MHz

Enhanced 16-bit parallel Host Interface (HID16)

• Supports a variety of microcontroller, microprocessor and DSP bus interfaces

PLLs

• Separate PPLs for SC140 Core, PPC bus and CPM

Process Technology

• First DSP manufactured using Motorola's new copper interconnect process technology
• .13 micron

 

Target Applications

The MSC8101 is intended for applications requiring very high performance, very large amounts of on-chip memory, and networking capabilities as:

• Third-generation wideband wireless infrastructure systems
• IP Telephony systems
• Multi-channel modem banks
• Multi-channel xDSL

Additional Information

Additional information on this announcement can be found at
www.motorola-dsp.com.

About Star*Core

Based in Atlanta, Georgia, the Star*Core Joint Design Center is a cooperative research and development initiative between Lucent Technologies and Motorola created to define next-generation digital signal processor (DSP) core technologies. Star*Core designs superior DSP architectures, cores, and development tools for the communications, consumer electronics and transportation industries. More information about Star*Core is available at
www.starcore-dsp.com.

About Motorola

As the world's #1 producer of embedded processors, Motorola Semiconductor Product Sector offers multiple DigitalDNA™ solutions which enable its customers in the consumer, networking and computing, transportation, and wireless communications markets, to create new business opportunities. Motorola's worldwide semiconductor sales were $7.3 billion (USD) in 1998. http://www.motorola.com/sps

Motorola is a global leader in providing integrated communications solutions and embedded electronic solutions. Sales in 1998 were $29.4 (USD) billion. http://www.motorola.com

Motorola is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. All other tradenames, trademarks, and registered trademarks are the property of their respective owners.

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For More Information:

READER CONTACT:
DSP Marketing
Greg Peloquin
480.413.5409

EDITORIAL CONTACTS:
Stacy Baniszewski
Motorola
480.413.5383
r25595@email.sps.mot.com

Phyllis Grabot
MS&L Global Technology
805.230.8205
pgrabot@msltech.com

 

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